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Electropolishing system and process

a technology of electroetching and electropolishing process, applied in the direction of electrolysis components, printed circuit manufacturing, manufacturing tools, etc., can solve the problems of loss of conductors, inability to accept conductor loss from within features, and the planarization capability of standard electroetching techniques is not as good as cmp

Inactive Publication Date: 2008-05-01
NOVELLUS SYSTEMS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a method and apparatus for electropolishing a surface of a conductive layer on a workpiece. The invention addresses the limitations of conventional electropolishing methods and provides alternative contacting means and electroetching techniques that can uniformly remove conductive films from a workpiece surface. The method involves immersing a contact electrode in a contact solution and contacting a portion of the surface of the conductive layer to define a contact region, immersing a process electrode in a process solution and contacting another portion of the surface of the conductive layer to define a process region, and applying an electrical potential between the contact electrode and the process electrode to electropolish the surface of the conductive layer within the process region. The invention also includes a mechanism for producing relative motion between the process region and the surface of the conductive layer to electropolish the whole surface of the conductive layer. The invention provides a more efficient and effective method for electropolishing conductive layers on workpieces.

Problems solved by technology

If planarization is not achieved, as the thickness of the conductor is reduced, presence of the step S causes loss of conductor from within the large trench.
As can be appreciated, such conductor loss from within features is not acceptable.
Planarization capability of standard electroetching techniques is not as good as CMP.
Advance of low-k material usage in wafer processing, however, is bringing new restrictions to the use of such contacts.
Low-k materials are relatively soft and mechanically weak.
Pressing metallic contacts and seals against conductive films deposited on low-k materials causes damage to such materials and may even cause loss of electrical contact since the conductive film over the damaged low-k layer may itself become discontinuous.

Method used

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Embodiment Construction

[0043] As will be described below, the present invention provides a method and a system to electroetch or electropolish a conductive material layer deposited on a surface of a semiconductor. The invention can be used with Electrochemical Mechanical Etching processes or conventional clectroetching systems. The present invention achieves electroetching of the conductive material through the combination of the use of a process solution and electrical contact elements that do not make physical contact to the workpiece surface.

[0044] Reference will now be made to the drawings wherein like numerals refer to like parts throughout. FIG. 2A shows a cross-sectional view of a portion of a workpiece 100a. The workpiece may be an exemplary portion of a preprocessed semiconductor wafer. As also shown in FIG. 2B in detail, a top layer 102a of the workpiece 100a may include a layer of conductive material such as electroplated copper. A bottom layer 104a of the workpiece may include an insulating l...

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Abstract

The present invention provides a process for electropolishing a conductive surface of a semiconductor wafer. During the process, a contact electrode in a contact solution contacts a contact region on surface of the conductive layer with the contact solution. Further, during the process a process electrode in a process solution contacts a process region on the conductive surface with the process solution while applying an electrical potential between the contact electrode and the process electrode to electropolish the surface of the conductive layer of the process region.

Description

RELATED APPLICATIONS [0001] This application claims priority from Provisional Application Serial No. 60 / 425,694 filed Nov. 12, 2002. This Application is a continuation in part of U.S. application Ser. No. 10 / 093,185, filed Mar. 5, 2002, (NT-003C) which is a continuation of U.S. Ser. No. 09 / 877,335 filed Jun. 7, 2001 (NT-003D), now U.S. Pat. No. 6,471,847, which is a divisional of U.S. Ser. No. 09 / 283,024 filed Mar. 30, 1999 (NT-003), now U.S. Pat. No. 6,251,235. This application is also a continuation in part of U.S. applications Ser. No. 09 / 685,934 filed Oct. 11, 2000 (NT-105) and U.S. Ser. No. 10 / 238,665, filed Sep. 20, 2002 (NT-001C1), which is a continuation of U.S. Ser. No. 09 / 607,567 filed Jun. 29, 2000, (NT-001D) which is a divisional of U.S. Ser. No. 09 / 201,929 filed Dec. 1, 1998, (NT-001) now U.S. Pat. No. 6,176,992, all incorporated herein by reference.FIELD [0002] The present invention generally relates to semiconductor integrated circuit technology and, more particularly...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): B23H3/00B23H5/08B24B37/20C25D5/02C25D5/06C25D5/22C25D7/12C25F3/02C25F7/00H01L21/00H01L21/288H01L21/321
CPCB23H5/08B24B37/20C25D5/02C25D5/06C25D5/22C25F3/02C25D7/123H01L21/2885H01L21/32115H01L21/32125H01L21/67075H01L21/6715C25F7/00H01L21/304C25F3/30
Inventor BASOL, BULENT M.TALIEH, HOMAYOUN
Owner NOVELLUS SYSTEMS
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