Electropolishing system and process

Abstract

The present invention provides a process for electropolishing a conductive surface of a semiconductor wafer. During the process, a contact electrode in a contact solution contacts a contact region on surface of the conductive layer with the contact solution. Further, during the process a process electrode in a process solution contacts a process region on the conductive surface with the process solution while applying an electrical potential between the contact electrode and the process electrode to electropolish the surface of the conductive layer of the process region.

Description

RELATED APPLICATIONS [0001] This application claims priority from Provisional Application Serial No. 60 / 425,694 filed Nov. 12, 2002. This Application is a continuation in part of U.S. application Ser. No. 10 / 093,185, filed Mar. 5, 2002, (NT-003C) which is a continuation of U.S. Ser. No. 09 / 877,335 filed Jun. 7, 2001 (NT-003D), now U.S. Pat. No. 6,471,847, which is a divisional of U.S. Ser. No. 09 / 283,024 filed Mar. 30, 1999 (NT-003), now U.S. Pat. No. 6,251,235. This application is also a continuation in part of U.S. applications Ser. No. 09 / 685,934 filed Oct. 11, 2000 (NT-105) and U.S. Ser. No. 10 / 238,665, filed Sep. 20, 2002 (NT-001C1), which is a continuation of U.S. Ser. No. 09 / 607,567 filed Jun. 29, 2000, (NT-001D) which is a divisional of U.S. Ser. No. 09 / 201,929 filed Dec. 1, 1998, (NT-001) now U.S. Pat. No. 6,176,992, all incorporated herein by reference.FIELD [0002] The present invention generally relates to semiconductor integrated circuit technology and, more particularly...

AI Technical Summary

Benefits of technology

[0014] The present invention overcomes the identified limitations of conventional electropolishing approaches and provides alternative contacting means and electroetching techniques that uniformly remove conductive films from a workpiece surface.

Problems solved by technology

If planarization is not achieved, as the thickness of the conductor is reduced, presence of the step S causes loss of conductor from within the large trench.

As can be appreciated, such conductor loss from within features is not acceptable.

Planarization capability of standard electroetching techniques is not as good as CMP.

Advance of low-k material usage in wafer processing, however, is bringing new restrictions to the use of such contacts.

Low-k materials are relatively soft and mechanically weak.

Pressing metallic contacts and seals against conductive films deposited on low-k materials causes damage to such materials and may even cause loss of electrical contact since the conductive film over the damaged low-k layer may itself become discontinuous.

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