Interconnect structures with ternary patterned features generated from two lithographic processes

Abstract

A method for fabricating an interconnect structure for interconnecting a semiconductor substrate to have three distinct patterned structures such that the interconnect structure provides both a low k and high structural integrity. The method includes depositing an interlayer dielectric onto the semiconductor substrate, forming a first pattern within the interlayer dielectric material by a first lithographic process that results in both via features and ternary features being formed in the interconnect structure. The method further includes forming a second pattern within the interlayer dielectric material by a second lithographic process to form line features within the interconnect structure. Hence the method forms the three separate distinct patterned structures using only two lithographic processes for each interconnect level.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to interconnect structures and methods to generate interconnect structures that are part of integrated circuits and microelectronic devices. The invention is based on the utilization of two distinct lithographic steps to create a structure having three distinct patterns. By repeating these processes, unique interconnect structures having enhanced mechanical or electrical properties are described. Exemplary methods for the fabrication of such structures are enclosed.[0003]2. Background Art[0004]The fabrication of Very-Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated circuits (ULSI) requires an interconnect structure comprised of metallic wiring that connects individual devices in a semiconductor chip, to one another. Typically, the wiring interconnect network consists of two types of features that serve as electrical conductors: line features that traverse a distance across the ...

AI Technical Summary

Benefits of technology

[0013]This invention relates to a novel interconnect structure that includes ternary features in a form of airgap structures, and support structures without air gaps for use in semiconductor integrated circuits (ICs), and to methods that are utilized in forming the interconnect structures. The novel interconnect structures are envisioned to be used within any semiconductor ICs, and particularly suited VLSI or ULSI designs that can benefit from reduced capacitances as a result of a lower k displayed by the interconnect structure, which semiconductors can be employed in any microelectronic device including: high speed microprocessors, application specific integrated circuits (ASICs), and memory storage. Incorporating the novel interconnect structure, and implementing the novel method for constructing the structures will realize a unique semiconductor IC structure with numerous advantages over structures that produced using current approaches including: reduced manufacturing costs, improved reliability, and enhanced device performance.

[0014]More specifically, the invention relates to the generation of novel interconnect structures where each level contains three distinct features, and that the three distinct features may be defined or incorporated into the IC structure using only two lithographic processes. Two of these features are the conventionally known conducting metal vias and lines used to transfer electrical signals across the chip in operation, as described above. More, and as mentioned above, providing the metallic lines and vias requires two lithographic processes. The third feature or ternary feature in accord with the invention provides an improvement in the interconnect structure that manifests in enhanced performance or reliability. The ternary feature exhibits its value in many ways, and in particular in view of its structural support as part of the interconnect structure. For that matter, its use allows the designer to use porous materials that might not normally display sufficient modulus and strength such as porous dielectrics. Alternatively, the ternary feature can be an airgap that is generated by from a sacrificial material that can be readily removed from interconnect structures during fabrication.

Problems solved by technology

Unfortunately, with the driving need to reduce the capacitance in interconnect structures, the mechanical robustness of the multilayer structures is being reduced by the use of these lower dielectric constant insulating materials.

This becomes even a greater concern as porosity is added into the interlayer dielectric, or when air gaps are incorporated since the strength of the interconnect structure can be greatly compromised by the effects of lower modulus and strengths of the dielectrics used.

Compromising the interconnect structures renders them susceptible to failure during the subsequent fabrication processes, affecting wafer yield.

Integration schemes involving such excessive and numerous processes can be cost prohibitive.

Lithographic processes can be especially expensive due to the combination of costs associated with tooling, masks, photoresists, developers, etc.

However, in general the conventional approaches involve two separate lithographic processes to generate the via and line patterns that are distinct and different.

For interconnects involving airgaps, this third separate lithographic process is generally required because airgaps must be omitted in regions within an interconnect design or structure where their inclusion would result in degraded reliability or mechanical failure of same.

Consequently, such approaches are generally not manufacturable however as a result of added lithographic process which can be cost prohibitive.

Furthermore, since three lithographic processes would be employed to add the airgap structures in specific portions of the interconnect structures, significant complications may result which may or may not be anticipated, including to name one, overlay misalignment resulting from the three separate patterning steps.

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