Semiconductor memory device

Abstract

A semiconductor memory device is constructed to include a memory cell formed by a plurality of transistors, wherein each of gate wiring layers of all of the transistors forming the memory cell is arranged to extend in one direction.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device such as a static random access memory (SRAM).[0003]In semiconductor memory devices, memory cells occupy a large portion of the device area. Hence, the memory cell is an important factor which determines the size, access speed and power consumption of the semiconductor memory device.[0004]2. Description of the Related Art[0005]First, a description will be given of a memory cell of a conventional 1-read-write / 1-read (1RW / 1R) RAM. FIG. 1 is a circuit diagram showing a memory cell of a conventional 1RW / 1R RAM. FIG. 2 is a diagram showing a layout of the memory cell of the conventional 1RW / 1R RAM. FIG. 3 is a diagram for explaining various symbols used to indicate a gate polysilicon layer, a gate contact layer, a source / drain contact region, a source / drain region, a well contact region, a cell frame...

AI Technical Summary

Benefits of technology

"The present invention provides a semiconductor memory device that solves problems of previous generations. It reduces the area occupied by a memory cell and guarantees stable operation by minimizing inconsistencies during production. The memory cell is formed by a plurality of transistors, where each gate wiring layer of all the transistors is arranged to extend in one direction. The transistors are arranged in a specific pattern to further reduce the area occupied by the memory cell and minimize the impact of inconsistencies. The transistors are made of N-channel MOS transistors or P-channel MOS transistors. The semiconductor memory device also includes signal lines and power lines arranged in a single wiring layer to reduce coupling capacitance and prevent noise and inversion of data. The memory cells are arranged in an array, and the source / drain of transistors from adjacent memory cells and the substrate contact may be used in common to further reduce the area occupied by the memory cell array."

Problems solved by technology

As a result, the access speed and the power consumption of the memory cell are affected by the different resistances, and the balance of the memory cell as a whole deteriorates.

Therefore, it is difficult to guarantee a stable operation of the semiconductor memory device.

As described above, in the conventional semiconductor memory device, there were problems in that it is difficult to reduce the area occupied by the memory cell, and that it is difficult to guarantee a stable operation of the semiconductor memory device due to the effects of the inconsistencies introduced during the production process.

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