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Input latch circuit having fuses for adjusting a setup and hold time

a technology of input latch and fuses, which is applied in the direction of pulse manipulation, pulse technique, instruments, etc., can solve the problems of large time required until, large error generation, and large time required to develop a devi

Inactive Publication Date: 2009-09-17
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the setup time and the hold time are not maintained for a given time in the latch circuit, the input data is not latched an error is generated as a result.
However, if the circuit is changed, a great deal of time is required until the circuit may be applied to a final wafer.
As a result, it takes a large amount of time to develop a device.

Method used

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  • Input latch circuit having fuses for adjusting a setup and hold time
  • Input latch circuit having fuses for adjusting a setup and hold time
  • Input latch circuit having fuses for adjusting a setup and hold time

Examples

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Embodiment Construction

[0027]FIG. 3 is a diagram showing an input latch circuit according to an embodiment of the present invention.

[0028]The input latch circuit of FIG. 3 comprises a setup time adjusting unit 100, a hold time adjusting unit 200, and a latch unit 300.

[0029]The setup time adjusting unit 100 selectively delays a clock signal CLK according to whether a fuse is cut and outputs the clock signal CLK to the latch unit 300. That is, when the fuse is not cut, the setup time adjusting unit 100 passes the clock signal CLK to the latch unit 300 without a delay. When the fuse is cut, the setup time adjusting unit 100 delays the clock signal CLK for a given period of time and outputs the delayed clock signal CLK to the latch unit 300.

[0030]The setup time adjusting unit 100 includes a setup fuse unit 110 and a setup adjusting unit120. The setup fuse unit 110 outputs setup adjusting signals FU_SU, FU_SUB for adjusting a setup time depending on whether the fuse is cut. The setup adjusting unit 120 selecti...

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PUM

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Abstract

An input latch circuit of a semiconductor device includes a setup time adjusting unit configured to selectively delay a clock signal and a hold time adjusting unit configured to selectively delay an input signal. The input latch circuit also includes a latch unit configured to latch an output signal of the hold time adjusting unit according to an output signal of the setup time adjusting unit. The input latch circuit changes and delays the clock signal and the input signal by cutting a fuse within the setup time adjusting unit and the hold time adjusting unit without requiring a change to a circuit in order to adjust a setup time and a hold time.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application claims priority to Korean Patent Application No. 10-2008-0023562, filed on Mar. 13, 2008, which is incorporated herein by reference in its entirety.BACKGROUND OF THE INVENTION[0002]The present invention relates generally to a semiconductor device, and more particularly, to a technology for adjusting a setup time and a hold time using external manipulation such as fuse cutting.[0003]A latch circuit refers to a circuit that maintains a signal inputted to a semiconductor device for a given period of time.[0004]FIG. 1 is a circuit diagram showing an input latch circuit according to the conventional art. FIG. 2 is a timing diagram illustrating the operation of the input latch circuit shown in FIG. 1.[0005]The input latch circuit according to the conventional art comprises a plurality of PMOS transistors P10˜P14, a plurality of NMOS transistors N11˜N15, and inverters I11 and I12.[0006]The latch circuit performs a latch o...

Claims

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Application Information

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IPC IPC(8): H03H11/26
CPCH03K2005/00234H03K3/356139G11C7/1087G11C7/22H03K19/096
Inventor JEONG, HOE GWON
Owner SK HYNIX INC