Deposition method and a deposition apparatus of fine particles, a forming method and a forming apparatus of carbon nanotubes, and a semiconductor device and a manufacturing method of the same

Abstract

A deposition method of fine particles, includes the steps of irradiating a fine particle beam formed by size-classified fine particles to an irradiated subject under a vacuum state, and depositing the fine particles on a bottom part of a groove structure formed at the irradiated subject.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a division of U.S. application Ser. No. 10 / 874,392, filed on Jun. 24, 2004 which is based upon and claims the benefit of priority from the prior Japanese Priority Patent Application No. 2003-187331 filed on Jun. 30, 2003, and Japanese Priority Patent Application No. 2003-298337 filed on Aug. 22, 2003, the entire contents of which are hereby incorporated by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a deposition method and a deposition apparatus of fine particles such as nano-particles having diameters less than about 30 to 90 nm, and a forming method and a forming apparatus of carbon nanotubes by using the fine particles as catalysts.[0004]Furthermore, the present invention relates to semiconductor devices having a channel or wires for which carbon nanotubes are used and manufacturing methods of the same, and more particularly, to a semiconductor device ha...

AI Technical Summary

Benefits of technology

The present invention provides a method and apparatus for depositing fine particles and forming carbon nanotubes with precise control over their growth. The method and apparatus can deposit particles on a bottom part of a groove structure and on a plane part, and can also control the growth of carbon nanotubes under a clean condition. This allows for easy control of the growth of carbon nanotubes and their electrical application. The invention also provides a semiconductor device with reduced resistance in perpendicular wiring parts and improved reliability. The semiconductor device includes a first conductive part, an interlayer insulating layer, a second conductive part, and a groove part including a catalyst layer and a carbon nanotube.

Problems solved by technology

First, although the above mentioned art is useful for piling the particles on the plane substrate, it is difficult to deposit the particles on the bottom part of the groove having a high aspect ratio, which is formed on the substrate with a size on the order of a micron or less. More particularly, as shown in FIG. 1, due to diffusion of the particles 301, the particles 301 are unevenly distributed and deposited at an entering part of a groove forming part 302. Because of this, it is difficult to lead the particles 301 to a bottom part 303. This tendency frequently occurs when making the sizes of the particles smaller. For example, this causes a big problem when the catalyst particles are deposited on the bottom part of the via hole in a case where the carbon nanotubes are applied as a via wiring of the semiconductor.

In addition, it is difficult to avoid exposing a surface of the particles to the air and such impurities.

Hence, it is difficult to generate particles having stable compositions.

The above mentioned impurities on the substrate and unstableness of the composition of the particles may cause problems in growing carbon nanotubes and controlling their diameters.

In addition, since the above mentioned process is a process substantially and easily exposed to the air, the surface of the substrate is easily oxidized and electric contact between the carbon nanotube after the growth and the substrate becomes worse.

Hence, it is difficult to apply the carbon nanotube to electric applications.

Thus, it is difficult to apply a conventional forming technology of the nano-particles to a process requiring a precise control of the carbon nanotube growth.

In addition, there are still a lot of problems in controlling the growth of the carbon nanotubes.

This causes a problem in that the upper wiring layer 103 and the lower wiring layer 101 are not electrically connected.

As the via hole forming part is narrowed and the number of the carbon nanotubes contributing to electric conductivity is reduced, unevenness of the via resistance becomes larger.

As a result, a problem such as wiring delay may occur in a case where the via forming part has a large via resistance.

Furthermore, in a case of the LSI having a lot of transistors wherein carbon nanotubes are used as a channel, unevenness of an electric current driving ability between the transistors occurs due to the unevenness of the internal and external diameters of the carbon nanotubes.

This causes a problem in that the capabilities of the entire LSI are reduced.

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