Optical Interconnection Arrangement For High Speed, High Density Communication Systems

Abstract

An optical interconnection arrangement for use in high data applications is presented that eliminates the need for extensive serialization/de-serialization (SERDES) functionality by utilizing pulse amplitude modulation (PAM) techniques to represent the data in the optical domain while utilizing a separate channel for transmitting an optical clock signal, eliminating the need for clock recovery circuitry on the receive end of the arrangement.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001]This application claims the benefit of U.S. Provisional Application No. 61 / 186,718, filed Jun. 12, 2009 and herein incorporated by reference.TECHNICAL FIELD [0002]The present invention relates to an optical interconnection arrangement and, more particularly, to an arrangement that reduces the need for extensive serialization / de-serialization (SERDES) functionality by utilizing pulse amplitude modulation (PAM) techniques in combination with a separate transmission channel for a clock signal.BACKGROUND OF THE INVENTION[0003]Due to the continuing demand for computing and networking applications, there is a growing demand for high performance computing (HPC) platforms, as well as large data centers. In either case, the interconnects between computer servers or network nodes have not been able to keep up with the growth in computing power within the chip or server. The bottlenecks include, but are not limited to, chip-to-chip communication po...

AI Technical Summary

Benefits of technology

[0008]The needs remaining in the prior art are addressed by the present invention, which relates to an optical interconnection arrangement and, more particularly, to an arrangement that reduces the need for extensive serialization / de-serialization (SERDES) functionality by utilizing pulse amplitude modulation (PAM) techniques and, additionally, incorporating a separate transmission channel for a clock signal, eliminating the need for clock recovery circuitry on the receive end of the arrangement.

Problems solved by technology

In either case, the interconnects between computer servers or network nodes have not been able to keep up with the growth in computing power within the chip or server.

The SERDES and clock recovery processes are problematic in that they consume a significant amount of power, while adding latency to a process where high speed operation is demanded and expected.

Images