Semiconductor device and method for fabricating the same
a technology of semiconductors and capacitors, applied in the direction of semiconductor devices, basic electric elements, electrical equipment, etc., can solve the problems of bunker defects, difficulty in securing the capacitance of capacitors, and defects in contact processes
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first embodiment
[0033]FIGS. 2A to 2E are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with the present invention.
[0034]Referring to FIG. 2A, an interlayer dielectric layer 22 is formed on a semiconductor substrate 21 defining first and second regions 201 and 202. The first region 201 may include a cell region of a memory device, and the second region 202 may include a peripheral circuit region and a core region of the memory device.
[0035]A plurality of contact plugs 23 are formed in the first region 201, so as to pass through the interlayer dielectric layer 22. The contact plugs 23 may include landing plugs or storage node contact plugs (SNC). Although not shown, when the contact plugs 23 are SNCs, a process of forming a transistor, including a word line, and a process of forming a bit line may typically be performed before the interlayer dielectric layer 22 is formed. The interlayer dielectric layer 22 is formed of an oxide layer. The contact plu...
second embodiment
[0071]FIG. 3F is a plan view of the semiconductor device according to the present invention, showing a state of the semiconductor device in which the buried guard ring 27 surrounds the edge of the first region 201 having the plurality of conductive patterns 30A formed therein. As such, since the buried guard ring 27 surrounds the first region 201, a bunker is not formed in the second region 202 during the dip-out process.
third embodiment
[0072]FIGS. 4A to 4F are cross-sectional views illustrating a method for fabricating a semiconductor device according to the present invention.
[0073]Referring to FIG. 4A, an interlayer dielectric layer 42 is formed on a semiconductor substrate 41 defining a cell region 401 and a peripheral circuit region 402. The cell region 401 and the peripheral circuit region 402 are regions which compose a memory device, such as DRAM.
[0074]A plurality of SNCs 43 are formed in the cell region 401 to pass through the interlayer dielectric layer 42. Although not shown, a process of forming a transistor, including a word line, and a process of forming a bit line may typically be performed before the SNCs 43 are formed. The interlayer dielectric layer 42 is formed of an oxide layer. The SNCs 43 are formed as follows. The interlayer dielectric layer 42 is etched using a storage node contact mask to form storage node contact holes, and a conductive layer, such as a polysilicon layer, is deposited and e...
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