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Optimization of manufacturing methodology: p-channel trench mos with low vth and n-type poly

a manufacturing method and mos technology, applied in the field of trench mos, can solve the problems of gate oxide not performing reliably, difficult to dope the polysilicon with p-type dopant ions, and inability to achieve in-situ p-type doping, etc., and achieve the effect of reducing the electric field

Active Publication Date: 2015-01-01
STMICROELECTRONICS INT NV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patent describes a method to create a shallow body region in a semiconductor material. By using a high-energy dopant implant, the electric field is reduced and breakdown can occur at a deeper level in the substrate. Additionally, the patent discusses the use of a polysilicon gate and in-situ doping with N type dopants to improve the performance of semiconductor devices. These technical effects provide thinner gate oxide and no nitridization, resulting in improved device performance.

Problems solved by technology

In some cases it can be very difficult to dope the polysilicon with P type dopant ions.
Non-in situ P type doping requires very large thermal budgets.
If the temperature is too high, the gate oxide can be contaminated with boron, leading to the possibility that the gate oxide will not perform reliably.
This can lead to poor conductivity of the gate electrode, causing poor performance of the trench MOSFET.
It can be very difficult to precisely control the temperature during diffusion of the boron into the gate electrode.
This additional step further increases the cost of manufacturing the trench MOSFET.

Method used

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  • Optimization of manufacturing methodology: p-channel trench mos with low vth and n-type poly
  • Optimization of manufacturing methodology: p-channel trench mos with low vth and n-type poly
  • Optimization of manufacturing methodology: p-channel trench mos with low vth and n-type poly

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Embodiment Construction

[0032]FIG. 2A is a cross-section of a semiconductor substrate 20 in an intermediate stage of forming a P-channel trench MOSFET therein according to one embodiment. The semiconductor substrate includes a highly doped drain region 24 and a less highly doped drain region 26. The drain regions 24, 26 are both doped with P type dopant atoms. In one example the drain regions 24, 26 are doped with boron atoms.

[0033]FIG. 2A further illustrates the doping of the body region above the drain region 26. N type dopant ions are implanted into the semiconductor substrate 20 by an ion implantation process. In the ion implantation process N type dopant atoms are given with an implantation energy toward the semiconductor substrate 20. The magnitude of the implantation energy determines the speed with which and the depth to which the dopant ions are driven toward the semiconductor substrate 20. The more energetic the ions are, the deeper they are implanted into the semiconductor substrate 20.

[0034]In ...

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Abstract

A method for forming a trench MOSFET includes doping a body region of the trench MOSFET in multiple ion implantation steps each having different ion implantation energy. The method further comprises etching the trench to a depth of about 1.7 μm.

Description

BACKGROUND[0001]1. Technical Field[0002]The present disclosure relates to the field of MOS transistors. The present disclosure relates more particularly to the field of trench MOSFET.[0003]2. Description of the Related Art[0004]Trench MOSFETs are type of vertical MOSFET in which the source region is at a top surface of a semiconductor substrate and the drain region is at a bottom surface of a semiconductor substrate. A body region is formed in the semiconductor substrate between the source and the drain. A trench is etched in the semiconductor substrate having sidewalls along the source and body regions. The trench is filled with polysilicon to form a gate electrode.[0005]For a PMOS device, it is beneficial to dope the polysilicon of the gate electrode with P type ions to reduce the value of the work function between the polysilicon and the silicon of the substrate. The threshold voltage for turning on the transistor is dependent on the work function of the transistor. The lower the...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/265H01L29/78H01L29/66H01L29/423H10B12/00
CPCH01L21/265H01L29/7827H01L29/66666H01L29/4232H01L21/26513H01L29/66734H01L29/7813H01L29/1095
Inventor YONG, YEAN CHINGFORTUNA, STEFANIA
Owner STMICROELECTRONICS INT NV