Method for Producing a Semiconductor Using a Vacuum Furnace

Abstract

A method of manufacturing a semiconductor includes providing a mold defining a planar capillary space; placing a measure of precursor in fluid communication with the capillary space; creating a vacuum around the mold and within the planar capillary space; melting the precursor; allowing the melted precursor to flow into the capillary space; and cooling the melted precursor within the mold such that the precursor forms a semiconductor, the operations of melting the precursor, allowing the precursor to flow into the capillary space, and cooling the melted precursor occurring in the vacuum.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This Application claims the benefit of and priority to U.S. Provisional Patent Application Ser. No. 61 / 812,078, filed Apr. 15, 2013, the contents of which is herein incorporated in its entirety by reference.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT[0002]Not ApplicableBACKGROUND OF THE INVENTION[0003]1. Field of Invention[0004]The present general inventive concept relates to the preparation of silicon-based semiconductor materials.[0005]2. Description of the Related Art[0006]The vast majority of wafers for solar cells for photovoltaic devices are made by processes which add substantial costs and impart defects that significantly reduce performance. Virtually all wafers are made by “wire sawing” wafers from larger ingots or blocks of silicon. The wire sawing has several defects and cost and yield elements. The vibration in the wire sawing action causes micro-cracks in the wafer which diminishes efficiency, causes downs...

AI Technical Summary

Benefits of technology

The patent describes a device that can create a vacuum to remove oxygen molecules from a certain space. The device also includes a tool for shaping semiconductor wafers that is made from a material that doesn't damage the wafer during the cooling process. The technical effects of this include a reduction in impurities in the space and a more precise tool for shaping semiconductor wafers.

Problems solved by technology

The vast majority of wafers for solar cells for photovoltaic devices are made by processes which add substantial costs and impart defects that significantly reduce performance.

The wire sawing has several defects and cost and yield elements.

The vibration in the wire sawing action causes micro-cracks in the wafer which diminishes efficiency, causes downstream failure from subsequent cracking; these micro cracks are typically 15-25 microns deep from both sides.

As the wafer is processed in downstream in line processing and assembly and shipping these stresses can put a moment on the crack and propagate a crack, which is especially costly as value is added to the wafer as a cell, as a module and even as it is installed making this defect very expensive.

The wire sawing is expensive in labor and in expendables and amortization of expensive equipment.

The “yield losses” of silicon from the wire sawing, including the cleaning of the ingot, the machining of the “loaves” and the losses from wire sawing often approach or exceed 70%.

The inescapable micro cracks limit how thin the wafers can be made, thus forcing the industry to use wafers thicker than otherwise desired.

This results in much reduced efficiency in the resulting solar cells along with a large volume of silicon cleaned from all surfaces because of the contamination therein from carbon and oxygen.

The quartz in this case is much purer than the rebonded fuses silica crucible, but there is much more flow of silicon in the crucible resulting in large amounts of oxygen distributed throughout the ingot thus reducing efficiency.

Because of the rates of diffusion in the silicon melts and the length of time at temperature, it is not possible to dope with boron, phosphorous or arsenic and maintain doping precision and accuracy required.

For this reason, an N type wafer has not been possible despite its advantages.

For these reasons these technical approaches have been compromised by very low yield on silicon, often 30% or less; very high costs for one use crucibles; high cost from long times and large masses at high temperature; high costs from wire sawing and its associated processes; low yield from downstream and in process failure from micro cracking; low efficiency due to contamination from processing; and an inability to make a very thin wafer.

Images