Method of forming a memory device structure and memory device structure

Abstract

The present disclosure provides a memory device structure including a wafer substrate, a magnetic tunnel junction (MTJ) formed by a first magnetic layer, a second magnetic layer, and a thin non-magnetic layer stacked along a first direction perpendicular to an upper surface of the wafer substrate above which the MTJ is formed, the non-magnetic layer being interposed between the first magnetic layer and the second magnetic layer, a first contact electrically coupled to the first magnetic layer, and a second contact electrically coupled to the second magnetic layer.

Description

BACKGROUND[0001]1. Field of the Disclosure[0002]In general, the present disclosure relates to a method of forming a memory device structure and to a memory device structure, and, more particularly, to the formation of memory device structures including magnetic random access memory techniques at advanced technology scales, such as 40 nm and beyond.[0003]2. Description of the Related Art[0004]At present, semiconductor and magnetic storage technologies represent some of the most commonly used data storage technologies. Semiconductor memory uses semiconductor-based circuit elements, such as transistors or capacitors, to store information, and common semiconductor memory chips may contain millions of such circuit elements. Both volatile and non-volatile forms of semiconductor memory exist. In modern computers, primary storage almost exclusively consists of dynamic volatile semiconductor memory or dynamic random access memory (DRAM). Since the turn of the century, a type of non-volatile ...

AI Technical Summary

Benefits of technology

This approach enables MRAM cells with improved thermal stability and reduced power consumption, facilitating higher integration densities and faster operation at smaller scales without the need for frequent refreshing or voltage pulses, thus addressing the limitations of existing MRAM technologies.

Problems solved by technology

For example, when considering memory devices of the next generation, that is, at technology nodes of 40 nm and beyond, e.g., at 28 nm and beyond, a scaling of DRAM cells requires a more frequent refreshing of the individual memory cells, resulting in greater power consumption of DRAM memory structures.

With regard to reading, flash and MRAM have very similar power requirements, whereas, for writing / rewriting, flash is rewritten using a large pulse of voltage (about 10V) that is stored up over time in a charge pump, which is both power hungry and time consuming.

In addition, the current pulse physically degrades the flash cells, which means that a flash memory can only be written to some finite number of times before it must be replaced.

This technique suffers from several drawbacks because it requires a fairly substantial current to generate the field and makes it less interesting for low power uses.

Furthermore, upon scaling down the cell in size, the risk of the induced field overlapping adjacent cells over a small area increases and, therefore, the risk of false writes increases.

There are concerns that the ‘classic’ type of MRAM cell will have difficulty at high densities due to the amount of current needed during writing, a problem that STT avoids.

The downside is the need to maintain spin coherence.

However, the materials with perpendicular magnetic anisotropy as used in the second concept are more expensive and critical to handle during the fabrication processes.

Images