Devices and methods of forming low resistivity noble metal interconnect

a noble metal and interconnect technology, applied in the field of semiconductor devices, can solve the problems of decreasing the performance of nodes and the increase of the resistivity of copper lines

Active Publication Date: 2017-11-30
GLOBALFOUNDRIES U S INC
View PDF6 Cites 6 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For 5 nm and beyond nodes, with the continually increasing demand for smaller circuit structures and faster device performance, copper line resistivity begins to climb, decreasing the performance of the nodes.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Devices and methods of forming low resistivity noble metal interconnect
  • Devices and methods of forming low resistivity noble metal interconnect
  • Devices and methods of forming low resistivity noble metal interconnect

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0021]Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting embodiments illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as to not unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating embodiments of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions and / or arrangements within the spirit and / or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure. Note also that reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers used throughout different figures designate the same or similar ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to view more

Abstract

Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

Description

FIELD OF THE INVENTION[0001]The present invention relates to semiconductor devices and methods of fabricating semiconductor devices, and more particularly, to devices and methods of forming low resistivity metal interconnects having noble metals.BACKGROUND OF THE INVENTION[0002]For 5 nm and beyond nodes, with the continually increasing demand for smaller circuit structures and faster device performance, copper line resistivity begins to climb, decreasing the performance of the nodes. The development of 5 nm nodes and smaller will likely require lowering the resistivity of the lines in the nodes.[0003]Therefore, it may be desirable to develop methods of fabricating nodes with lines that have a lower resistivity than copper at such a small size.BRIEF SUMMARY[0004]The shortcomings of the prior art are overcome and additional advantage are provided through the provisions, in one aspect, a method that includes, for instance: obtaining an intermediate semiconductor interconnect device hav...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(United States)
IPC IPC(8): H01L23/522H01L21/285H01L21/768H01L21/02H01L23/532H01L23/528
CPCH01L23/5226H01L23/53252H01L23/528H01L21/76864H01L21/7685H01L21/02244H01L21/7682H01L21/28568H01L21/28556H01L21/2855H01L21/7684H01L21/76838H01L23/53242H01L21/76834H01L21/76856H01L21/76865H01L23/5222H01L23/53295
Inventor ZHANG, XUNYUANMONT, FRANK W.RYAN, ERROL TODD
Owner GLOBALFOUNDRIES U S INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products