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Image processing circuit and semiconductor integrated circuit

a technology of image processing circuit and integrated circuit, which is applied in the direction of program control, sustainable buildings, instruments, etc., can solve the problems of increasing the number of required flip-flop circuits, increasing the power consumption of the switching operation of each flip-flop circuit, and wasting the switching operation of the synchronization register, so as to reduce power consumption

Inactive Publication Date: 2016-09-13
SOVEREIGN PEAK VENTURES LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This configuration allows for reduced power consumption in pipeline processing by minimizing unnecessary clock signal operations and avoiding increased circuit resources, effectively performing image processing with lower power consumption while maintaining functionality.

Problems solved by technology

However, in the pipeline processing, as the content of the image processing becomes more complicated, the number of required flip-flop circuits increases.
As a result, the power consumption in the switching operation of each flip-flop circuit increases.
In a case where the input value and output value of the synchronization register are the same, since the value to be held does not change, it can be said that the switching operation of the synchronization register is a useless operation.
In a case where the input value and output value of a flip-flop circuit in an image processing circuit are the same, it can be said that the switching operation is a useless operation.

Method used

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  • Image processing circuit and semiconductor integrated circuit
  • Image processing circuit and semiconductor integrated circuit
  • Image processing circuit and semiconductor integrated circuit

Examples

Experimental program
Comparison scheme
Effect test

embodiment 1

[0032]In the following, an explanation about an image processing circuit according to Embodiment 1 of the present invention is given in order from the overall configuration to specific configurations.

[0033]

[0034]First, the overall configuration of the image processing circuit is described.

[0035]FIG. 1 is a configuration illustrating an example of a configuration of the image processing circuit according to the present embodiment.

[0036]In FIG. 1, image processing circuit 100 is an apparatus that reads and receives image data from an external memory (not illustrated) and performs various kinds of conversion processing (image processing) on the input image data. For example, image processing circuit 100 is mounted on a semiconductor integrated circuit in a digital camera or a portable information terminal.

[0037]Here, in the present embodiment, it is assumed that image data input to image processing circuit 100 is image data having pixel data of N bits (N is an integer equal to or great...

embodiment 2

[0120]Embodiment 2 of the present invention is an example of stopping the operation of a comparison circuit in a case where the operation of the comparison circuit is not necessary.

[0121]

[0122]FIG. 10 is a configuration diagram illustrating an example of the configuration of an image processing circuit according to the present embodiment, which corresponds to FIG. 1 in Embodiment 1. The same reference numerals are assigned to the same parts as those illustrated in FIG. 1 and explanation thereof is omitted.

[0123]In FIG. 10, in addition to the configuration illustrated in FIG. 1, image processing circuit 100a has correlation level detection section 108a disposed between input DMA 101 and first line buffers 102. Moreover, image processing circuit 100a has control section 110a including comparison processing mode control section 111a, in place of control section 110 in FIG. 1.

[0124]Correlation level detection section 108a acquires the correlation level indicating the matching frequency ...

embodiment 3

[0160]Embodiment 3 of the present invention is an example where, by using the output of one comparison circuit for the other, the operation of the other comparison circuit is stopped between the left-eye image data and right-eye image data of a stereo image.

[0161]

[0162]FIG. 13 is a configuration diagram illustrating an example of the configuration of an image processing circuit according to the present embodiment, which corresponds to FIG. 1 in Embodiment 1. The same reference numerals are assigned to the same parts as FIG. 1 and the explanation thereof is omitted.

[0163]In FIG. 13, image processing circuit 100b according to the present embodiment receives left-eye image data and right-eye image data. The left-eye image data is data of the left-eye image (L image) of a stereo image (3D image). The right-eye image data is data of the right-eye image (R image) of the stereo image.

[0164]Image processing circuit 100b has two each of first line buffer 102, first filter 103 and second filt...

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PUM

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Abstract

This image processing circuit performs, with reduced power consumption, pipeline processing of image data. This image processing circuit has an image processing unit which performs pipeline processing of image data having N-bit pixel data. The image processing unit has a pipeline register (400) having upper bit flip-flop circuits (401), lower-order bit flip-flop circuits (402), a comparison circuit (403) which determines whether the input values and the output values of the upper bit flip-flop circuits (401) are the same, and a clock gating control circuit (404) which controls supply of the clock signal such that, when the aforementioned input and output values are the same, the clock signal is not supplied to the upper bit flip-flop circuits (401). The pipeline register (400) does not have a circuit for controlling supply of the clock signal to the lower 1-bit flip-flop circuits (402), and holds pixel data or calculation results during pipeline processing.

Description

TECHNICAL FIELD[0001]The present invention relates to an image processing circuit and a semiconductor integrated circuit that include a pipeline register and perform image processing on image data by pipeline processing.BACKGROUND ART[0002]Color image data or the like is image data formed of pixel data of N bits (N is an integer equal to or greater than two). As image processing on such image data, data conversion processing is widely performed for image quality improvement, expansion, reduction and the like. The image data is normally pixel value data acquired by scanning the image for every pixel line. As a method for realizing high-speed processing, pipeline processing (parallel processing) is used for the data conversion processing (image processing) on such image data. In this pipeline processing, many pipeline registers are used.[0003]The pipeline register used for the image processing normally has a plurality of flip-flop circuits which are provided per bit of the image data....

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G06T1/20G06F1/32G06F9/28
CPCG06T1/20G06F1/3237G06F9/28G06T2200/28Y02B60/1221G06F9/3869Y02D10/00
Inventor HOSHINO, MASASHIHARADA, MASAAKI
Owner SOVEREIGN PEAK VENTURES LLC