Spacer-type thin-film polysilicon transistor for low-power memory devices

Abstract

The cross-sectional area of a thin-film transistor (TFT) is decreased in order to minimize bitline to supply leakage of the TFT. This is accomplished by utilizing a spacer etch process to manufacture a TFT having a very narrow and thin channel in a controllable manner. The spacer dimensions of the TFT may be adjusted by simply modifying the thicknesses of the poly gate and the channel poly. The channel thickness is limited by the thickness of the deposited channel polysilicon which may be as thin as approximately 300 Å to 500 Å, and the channel width of the TFT corresponds to the height of the spacer etched along the polysilicon gate of the device which may be as small as approximately 0.15 to 0.25 μm.

Description

[0001]This application is a continuation application of U.S. patent application Ser. No. 09 / 334,877, filed Jun. 17, 1999, and is now abandoned, which is a reissue of U.S. patent application Ser. No. 08 / 521,709, filed Aug. 31, 1995, which is now U.S. Pat. No. 5,640,023, issued Jun. 17, 1997.BACKGROUND OF THE INVENTION[0002]The present invention relates generally to integrated circuit memory devices, and more specifically to integrated circuit memory devices which employ thin-film transistor (TFT) technology.[0003]Thin-film transistors (TFTs) are becoming the load devices of choice in many integrated circuit memory devices, particularly in static random access memory (SRAM) cells. TFTs are superior to standard polysilicon resistor load devices, in that TFTs have an inherently lower OFF current—an advantage which is particularly relevant in low—and zeropower SRAM applications which feature extended battery operation. In spite of this advantage, however, the bitline to supply (Vcc) leak...

AI Technical Summary

Benefits of technology

[0005]It would be advantageous in the art to minimize bitline to supply (Vcc) leakage of thin-film transistors (TFTs).

[0006]It would further be advantageous in the art to be able to reduce the cross-sectional area of a TFT channel in order to minimize bitline to supply (Vcc) leakage of a thin-film transistor (TFT).

[0007]Therefore, according to the present invention, the cross-sectional area of a thin-film transistor (TFT) is decreased in order to minimize bitline to supply leakage of the TFT. This is accomplished by utilizing a spacer etch process to manufacture a TFT having a very narrow and thin channel in a controllable manner. The spacer dimensions of the TFT may be adjusted by simply modifying the thicknesses of the poly gate and the channel poly. The channel thickness is limited by the thickness; of deposited channel polysilicon which may be as thin as approximately 300 Å to 500 Å, and the channel width of the TFT corresponds to the height of the spacer etched along the polysilicon gate of the device which may be as small as approximately 0.15 to 0.25 μm.

[0008]A first preferred embodiment of the present invention employs at least two polysilicon layers to effect a spacer etch process which allows the cross-sectional area of a transistor channel of a TFT to be minimized in a controllable manner, thereby reducing the bitline to voltage supply leakage of the TFT. The first preferred embodiment provides planarization as an option. A second preferred embodiment of the present invention also utilizes a spacer etch process by selective etching a poly spacer of a spacer-TFT load structure formed around a first poly gate layer in order to achieve the desired channel length. The second preferred embodiment offers the advantage of requiring just two polysilicon layers; planarization is not required.

Problems solved by technology

In spite of this advantage, however, the bitline to supply (Vcc) leakage of TFTs designed and fabricated in state-of-the-art technology is still too significant to enable battery operation of high-density memory devices, such as SRAMs, over an extended period of time.

Unfortunately, the resultant polysilicon grain size of these layers is also very small.

As would be anticipated, this difference between the width dimension and other CDs of the memory device places considerable pressure on the photolithography aspect of manufacturing and thus makes manufacturing of a device using such geometries very difficult.

This results in process complications which do not render a viable manufacturing approach.

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