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Multiple chip packaging arrangement

A multi-chip packaging and chip technology, applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve the problem of increasing the overall thickness, width and volume of the multi-chip packaging structure 10, and the poor heat dissipation effect of the multi-chip packaging structure 10 Huge, heat can not be effectively dissipated and other issues

Active Publication Date: 2007-10-17
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] It should be noted that, based on the working space for wire bonding of the wires 14a-16b, the thickness of the adhesive layers 13a and 13b must be large enough, and the encapsulant 17 must cover the wires 14a-16b, resulting in the overall thickness of the multi-chip package structure 10 , width and volume increase a lot
In addition, since the chips 12a-12c are arranged on the front surface of the substrate 11, and the front surface of the encapsulant 17 must be higher than the active surface of the chip 12c and the highest turning point of the wires 16a and 16b, the heat generated by the chips 12a-12c cannot be effectively The ground dissipates to the outside world, greatly affecting the heat dissipation effect of the multi-chip packaging structure 10

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0031] Please refer to FIG. 2A , which shows a cross-sectional view of a multi-chip package structure according to Embodiment 1 of the present invention. In FIG. 2A, the multi-chip package structure 20a includes a lead frame 29a, an encapsulant 32a, several conductive materials and several chips, such as four chips 22, two first conductive materials 27 and two second conductive materials. 28. As shown in Figure 2B and Figure 2C, each chip 22 has a relative active surface 22a and a non-active surface 22b, several chip through holes 22c and several insulating layers 22d, and the peripheral part of the active surface 22a of each chip 22 has Several welding pads 22e. Each through-chip hole 22c of each chip 22 runs through each pad 22e and the non-active surface 22b, and each insulating layer 22d of each chip 22 is coated on the inner wall of each through-chip hole 22c other than each pad 22e. Please refer to FIG. 2A again, two chips 22 are sequentially glued and stacked to form ...

Embodiment 2

[0035]Please refer to FIG. 2E , which is a cross-sectional view of a multi-chip packaging structure according to Embodiment 2 of the present invention. In FIG. 2E , the difference between the multi-chip package structure 20b of the present embodiment and the multi-chip package structure 20a of the first embodiment lies in the structure of the lead frame 29b , and the rest of the same components continue to use the same reference numerals and will not be described again. Each pin 21a of the lead frame 29b has a pin through hole 21d, and each pin through hole 21d corresponds to each first chip group through hole 26a and each second chip group through hole 26b, so that each first conductive material 27 or Each second conductive material 28 is filled in each pin through hole 21d.

Embodiment 3

[0037] Please refer to FIG. 2F , which is a cross-sectional view of a multi-chip packaging structure according to Embodiment 3 of the present invention. In FIG. 2F , the difference between the multi-chip package structure 20c of the present embodiment and the multi-chip package structure 20a of the first embodiment lies in the structure of the lead frame 29c. The first pin surface 21b and the second pin surface 21c of each pin 21a of the lead frame 29c have conductive bumps 30a and 30b respectively, and each conductive bump 30a is embedded in each first chip set through hole 26a, and is connected with Each first conductive material 27 is electrically connected to increase the effect of positioning the first chipset 23a on the lead frame 29c. In addition, each conductive bump 30b is embedded in each second chip set through hole 26b, and is electrically connected with each second conductive material 28, so as to enhance the positioning effect of the second chip set 23b on the le...

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Abstract

This invention relates to multiple chips sealed structure, which comprises several chips, one wire rack and several conductive materials. The chip surface has several solder pads and the chip hole passes the solder pad and the insulation layer is coated on the inner wall of the chip hole besides solder pad. The chips are orderly added with two sets of chips with several chip sets hole. The wire rack has several lead legs with two lead leg relative surfaces, which are relative to the connection surface of each chip set. The conductive materials are filled in all chips set hole to connect each chip solder pad and the lead legs.

Description

【Technical field】 [0001] The present invention relates to a packaging structure of semiconductor components, and in particular to a packaging structure of multi-chips. 【Background technique】 [0002] As far as the current semiconductor packaging technology is concerned, a package of colloid is usually used to cover multiple chips to achieve more than double the capacity or more functional requirements, which is the so-called multi-chip packaging structure. For example, by combining two 8MB memory chips into a package, a package structure with a 16MB capacity can be obtained, and there is no need to directly manufacture a single chip with a 16MB capacity. [0003] Please refer to FIG. 1 , which is a cross-sectional view of the multi-chip package structure disclosed in US Patent No. 5,323,060. In FIG. 1 , the multi-chip package structure 10 includes a substrate 11 , chips 12 a , 12 b and 12 c , adhesive layers 13 a and 13 b , wires 14 a , 14 b , 15 a , 15 b , 16 a and 16 b an...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/58H01L21/60H01L25/065
CPCH01L2224/16H01L2224/48091H01L2924/00014
Inventor 蔡振荣林志文
Owner MACRONIX INT CO LTD