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Condition presetting construction based D trigger having scanning test function

A scanning test and flip-flop technology, which is applied in the direction of electronic circuit testing, electrical components, pulse generation, etc., can solve the problem of extreme asymmetry of the rising edge delay and falling edge delay of the output terminal of the flip-flop circuit.

Inactive Publication Date: 2007-11-07
TSINGHUA UNIV
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  • Abstract
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Problems solved by technology

However, the problem with the SAFF_CP circuit is that since the output latch circuit adopts a cross-coupled NAND2 (NAND2: two-input NAND gate) structure, the delay of the rising edge and falling edge of the output of the flip-flop circuit will be extremely different. Symmetry, which poses potential problems for the use of circuit cells

Method used

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  • Condition presetting construction based D trigger having scanning test function
  • Condition presetting construction based D trigger having scanning test function
  • Condition presetting construction based D trigger having scanning test function

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Embodiment Construction

[0074] The technical solution of the present invention to solve the technical problem is: the testable flip-flop FFSDHD1X_SCB_FCS based on the conditional prefill structure proposed by the present invention, as shown in FIG. 4 . The FFSDHD1X_SCB_FCS flip-flop has the feature of using conditional precharge technology to reduce the power consumption of the flip-flop circuit itself, and also has testable functions.

[0075] The structure on the right side in Figure 4 is a basic flip-flop based on the conditional precharge structure. DI is the D signal input terminal of the basic flip-flop, which is a D flip-flop triggered by a rising edge. Its working principle is as follows: the clock signal CLK and the input The data signal DI forms an "OR" logic and is connected to the gate of the PMOS transistor MP1, while the clock signal CLK and the input data signal D b Form OR logic and connect to the gate of PMOS transistor MP2. When CLK is at a high level, both MP1 and MP2 are turned o...

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Abstract

This invention relates to one D trigger with scanning function based on pre-charging structure in the trigger field, which is characterized by comprising the control circuit, the first and second locking memory serried orderly, wherein, the control circuit uses the transmission gate as the front control logics; the first locking memory adopts conditional pre-charging circuit controlled by the input data signals; the second locking memory is composed of two independent circuit parameter single clock memory; the two locking memories are connected to one inverter as maintainer.

Description

technical field [0001] The technical field of direct application of "D flip-flop with scan test function based on conditional pre-charge structure" is the design of low-power flip-flop circuit with scan test function based on conditional pre-charge structure. The proposed circuit is a kind of CMOS flip-flop circuit unit applicable to low-power clock signal network technology. Background technique [0002] With the advancement of CMOS integrated circuit manufacturing technology, the scale and complexity of integrated circuits are increasing day by day, and the power consumption and heat dissipation of integrated circuits have been paid more and more attention from industry and academia. Based on the current integrated circuit design style, in large-scale digital circuit systems, the energy consumed by the clock network accounts for a high proportion of the total energy consumption of the entire circuit; among them, in the working state of the circuit, the energy consumed in t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K3/012H03K3/037H03K3/356G01R31/28
Inventor 杨华中高红莉乔飞汪蕙
Owner TSINGHUA UNIV
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