Test device for masiac storage

An embedded memory and test device technology, applied in static memory, instruments, etc., can solve problems such as waste of chip area and power consumption, and achieve the effect of saving area and power consumption, and saving chip area and power consumption

Inactive Publication Date: 2007-12-19
VIMICRO CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It can be seen that the more memory modules in the prior art, the more corresponding address generators, vector generators and finite state machines, resulting in a large waste of chip area and power consumption.

Method used

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  • Test device for masiac storage
  • Test device for masiac storage
  • Test device for masiac storage

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0022]Referring to Fig. 2, a kind of testing device of embedded memory, comprises 2 groups of memory modules 1a, 1b and the embedded memory test control module 2 that receives chip external pin start signal, memory module 1a includes multiplex switch 3a and memory 4a , the memory module 1b includes a multiplex switch 3b and a memory 4b. The depth of the memory 1a is greater than the depth of the memory 1b. The output terminal of the multiplex switch 3a is connected to the input terminal of the memory 4a. The output end of the multiplex switch 3b is connected to the input end of the memory 4b. The embedded memory test control module 2 includes two response analyzers 8a, 8b and two vector generators 7a, 7b corresponding to the two groups of memory modules 1a, 1b. Described embedded memory test control module 2 comprises an address generator 5 and a finite state machine 6, and described address generator 5 is the address generator corresponding with memory module 1a, and descri...

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PUM

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Abstract

The present invention relates to test device for mosaic storage and belongs to the field of storage test. The present invention can save chip area and power consumption. The mosaic storage testing and controlling module includes one address generator, one limited state machine and one vector generator. The address generator corresponds to the deepest memory in the N memory modules; and the vector generator corresponds to the memory with great bit width in the N memory modules. When the address generator has addressing depth exceeding that of the address generator during addressing the N memory modules, the address generator sends inhibition signal to the memory modules with greater depth to inhibit the multiplexer to lead the vector to the memory modules and sends inhibition signal to corresponding responding analyzers to inhibit their work.

Description

technical field [0001] The invention relates to the field of memory testing, in particular to a testing device for embedded memory. Background technique [0002] Large, complex circuits often contain multiple parts of logic that are difficult to test, requiring significant test generation time, ATE (Automated Test Equipment) memory and ATE test time, all of which are very expensive but necessary for testing with the ATPG method. In addition, because memory defect types are different from general logic defect types, and memory is deeper in larger-scale designs, ATPG (Automatic Test Pattern Generation) usually cannot provide a complete memory test solution, while the embedded Type Memory Test Technology (MBIST) can solve these problems. BIST (Build In Self Test built-in self-test circuit) can provide a memory test solution without sacrificing the quality of detection. In many cases, the BIST structure can completely eliminate or minimize the generation of external test vecto...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/00
Inventor 周芬周天夷
Owner VIMICRO CORP
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