Test device for masiac storage

Abstract

The present invention relates to test device for mosaic storage and belongs to the field of storage test. The present invention can save chip area and power consumption. The mosaic storage testing and controlling module includes one address generator, one limited state machine and one vector generator. The address generator corresponds to the deepest memory in the N memory modules; and the vector generator corresponds to the memory with great bit width in the N memory modules. When the address generator has addressing depth exceeding that of the address generator during addressing the N memory modules, the address generator sends inhibition signal to the memory modules with greater depth to inhibit the multiplexer to lead the vector to the memory modules and sends inhibition signal to corresponding responding analyzers to inhibit their work.

Description

technical field [0001] The invention relates to the field of memory testing, in particular to a testing device for embedded memory. Background technique [0002] Large, complex circuits often contain multiple parts of logic that are difficult to test, requiring significant test generation time, ATE (Automated Test Equipment) memory and ATE test time, all of which are very expensive but necessary for testing with the ATPG method. In addition, because memory defect types are different from general logic defect types, and memory is deeper in larger-scale designs, ATPG (Automatic Test Pattern Generation) usually cannot provide a complete memory test solution, while the embedded Type Memory Test Technology (MBIST) can solve these problems. BIST (Build In Self Test built-in self-test circuit) can provide a memory test solution without sacrificing the quality of detection. In many cases, the BIST structure can completely eliminate or minimize the generation of external test vecto...

AI Technical Summary

Problems solved by technology

It can be seen that the more memory modules in the prior art, the more corresponding address generators, vector generators and finite state machines, resulting in a large waste of chip area and power consumption.

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