Formation of lattice-tuning semiconductor substrates

Abstract

A method of forming a lattice-tuning semiconductor substrate comprises the steps of defining parallel strips of a Si surface by the provision of spaced parallel oxide walls ( 2 ) on the surface, selectively growing a first SiGe layer on the strips such that first dislocations ( 3 ) extend preferentially across the first SiGe layer between the walls ( 2 ) to relieve the strain in the first SiGe layer in directions transverse to the walls ( 2 ), and growing a second SiGe layer on top of the first SiGe layer to overgrow the walls ( 2 ) such that second dislocations form preferentially within the second SiGe layer above the walls ( 2 ) to relieve the strain in the second SiGe layer in directions transverse to the first dislocations ( 3 ). The dislocations so produced serve to relax the material in two mutually transverse directions whilst being spatially separated so that the two sets of dislocations cannot interact with one another. Thus the density of threading dislocations and the surface roughness is greatly reduced, thus enhancing the performance of the virtual substrate by decreasing the disruption of the atomic lattice that can lead to scattering of electrons in the active devices and degradation of the speed of movement of the electrons.

Description

technical field [0001] The present invention relates to the fabrication of lattice-tuned semiconductor substrates and in particular, but not exclusively, to the fabrication of stress-free silicon / germanium (SiGe) "virtual substrates" suitable for strained silicon or SiGe activation layer and the growth of strain-free III-V semiconductor active layers in which active semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) can be fabricated. Background technique [0002] It is currently known to epitaxially grow strained silicon layers on Si wafers with an unstressed SiGe buffer layer interposed between them, and to fabricate semiconductor devices such as MOSFETs in strained silicon layers to enhance the performance of semiconductor devices. The buffer layer is provided to increase the lattice spacing relative to that of the underlying Si substrate, and is often referred to as a dummy substrate. [0003] It is currently known that an alloy o...

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Problems solved by technology

However, this technique produces a non-planar surface, which is totally unsuitable for bonding semiconductor devices over a wide area of ​​the substrate surface

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