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Dense array structure for non-volatile semiconductor memories

A memory array and semiconductor technology, applied to non-volatile memory, to manufacture this kind of dense array structure, in the field of dense array structure of memory elements, which can solve the problems of large array yield loss and other issues

Inactive Publication Date: 2008-10-01
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] A disadvantage of the above prior art cell structures is that they use zigzag patterns which inevitably lead to large cells. This is due to the photolithography process used in the fabrication of such devices: it is easier to pattern straight lines than to pattern zigzag lines .Furthermore, the zigzag pattern can lead to yield loss for large arrays because of the risk of sub-circuiting

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  • Dense array structure for non-volatile semiconductor memories
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  • Dense array structure for non-volatile semiconductor memories

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Embodiment Construction

[0036] The present invention is described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto but only by the claims. The drawings described are only illustrative and not limiting. The following references are made to process commonly used silicon semiconductors, but the invention is not limited thereto and also includes within its scope other semiconductor systems such as those based on germanium, silicon / germanium, gallium arsenide, etc. Those skilled in the art will appreciate Although references are made to materials conventionally used in silicon processing, equivalent materials in other semiconductor systems are known to those skilled in the art.

[0037] Throughout this specification, the terms "horizontal", "vertical", and "diagonal" are used only to provide a coordinate system and to simplify explanation. They do not have to, but can, refer to the actual physical orientation of the device. Also, the te...

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Abstract

The present invention describes an array structure ( 10 ) for non-volatile semiconductor memory elements ( 14, 16 ) with a high area density. This high density is obtained by the combination of a commonly used virtual ground scheme and a 2-dimensional array of memory elements ( 14, 16 ). Wordlines ( 18, 20 ) connecting memory elements ( 14, 16 ) in a row or a column cross each other at insulated cross-points ( 22 ). Furthermore, the invention describes a possible fabrication process for such memory arrays.

Description

technical field [0001] The present invention relates to the field of a nonvolatile semiconductor memory such as a floating gate memory and a method of operation thereof. More particularly, the present invention relates to such dense array structures of memory elements, nonvolatile memory devices including such dense array structures Memories, and methods of fabricating such dense array structures. Background technique [0002] Non-volatile memory (NVM) is widely used in various commercial and military electronic devices and equipment, such as cellular phones, radio communications, and digital cameras. The market for these electronic devices still requires low voltage, low power consumption, and reduced chip size. device. [0003] Flash memory consists of a grid of columns and rows with MOSFETs at each intersection, the MOSFETs have one (or more) floating gates (FG) between the control gate (CG) and the channel region, the floating gate and The control gates are separated b...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/115H01L21/8247H01L21/8246G11C16/04H01L29/788H01L29/792H10B20/00H10B69/00
CPCG11C16/0416H01L27/11521H01L27/11519H01L27/115H01L27/11568H10B41/10H10B69/00H10B41/30H10B43/30H01L27/04
Inventor M·J·范杜尤伦R·T·F·范沙伊克
Owner NXP BV