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ESD protection for high voltage applications

An electrostatic discharge and static electricity technology, applied in the direction of circuits, electrical components, electrical solid devices, etc., can solve problems such as excessive layout overhead

Active Publication Date: 2009-02-04
AVAGO TECH INT SALES PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

MOS-based ESD protection devices suffer from characteristic high threshold voltage and channel impedance of high-voltage MOS, which leads to excessive layout overhead (layout overhead)
Diode-based ESD protection devices suffer from parasitic series resistance inherent in high-voltage processing technology, which also results in excessive layout overhead
Another obstacle in the design of high-voltage ESD protection is the assembly of high-voltage resistant resistors and capacitors in the ESD protection circuit

Method used

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  • ESD protection for high voltage applications
  • ESD protection for high voltage applications
  • ESD protection for high voltage applications

Examples

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Embodiment Construction

[0067] 1A and 1B illustrate a doped semiconductor device 100 with a lower breakdown voltage. As shown in FIG. 1A , the doped semiconductor device 100 includes a conventional doped well 102 and a doped body 104 . Compared with the doped base 104 , the conventional doped well 102 has a higher doping concentration and a shallower junction depth. The concentration level of conventional doped wells is usually 10 17 / cm 3 . The doped matrix 104 also has a relatively high doping concentration. However, the polarity of the dopant applied to the doped body 104 is opposite to that applied to the conventional doped well 102 . For example, if the conventional doped well 102 is a p-type material, then the doped body 104 is an n-type material. Alternatively, if the conventional doped well 102 is an n-type material, then the doped body 104 is a p-type material. In each case of doping, the conventional doped well 102 is in intimate contact with the doped body 104, forming a pn junction....

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Abstract

An ESD device includes a low-doped well connected to a first contact, and a diffusion region connected to a second contact. The dopant polarity of the matrix between the low doped well and the diffusion region is opposite to that of the low doped well and the diffusion region. The distance between the low-doped well and the diffusion region determines the trigger voltage of the ESD device. When a reverse bias is applied to the ESD device, a depletion region is formed between the low doped well and the substrate. When the reverse bias causes the depletion region to come into contact with the diffusion region, a current discharge path is formed between the first contact and the second contact. By connecting to the second contact, the base is biased. Optionally, an additional diffusion region of the same polarity of the dopant is connected to the third contact to bias the body.

Description

technical field [0001] The present invention generally relates to electrostatic discharge (ESD) protection. More particularly, the present invention provides ESD protection for high voltage integrated circuits (ICs). Background technique [0002] ESD protection is often difficult to provide in high voltage ICs with higher voltage tolerances. The breakdown voltage of the high-voltage device must be higher than the operating voltage of the high-voltage IC. ESD protection must provide an ESD trigger voltage that is higher than the operating voltage of the high-voltage IC and lower than the breakdown voltage of the high-voltage device. The operating voltage of high-voltage ICs is usually close to the breakdown voltage of high-voltage devices, so that the allowable range of ESD trigger voltage is very narrow and difficult to achieve. [0003] Conventional IC devices, such as metal oxide semiconductors (MOSs), field effect transistors (MOSFETs) and bipolar junction transistors ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/60
CPCH01L2924/0002H01L2924/00
Inventor 艾格尼丝·N·伍
Owner AVAGO TECH INT SALES PTE LTD