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BiCMOS compatible JFET device and method of manufacturing same

A device, bipolar device technology, applied in the field of BiCMOS process, which can solve the problems of increasing the complexity and cost of standard BiCMOS process

Inactive Publication Date: 2009-07-29
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, additional steps are required in the fabrication of JEFETs, including an implant step to form the top gate region and another implant step to create the JFET channel region, which must be performed separately from the steps used to fabricate vertical bipolar transistors. steps, thereby increasing the complexity and cost of standard BiCMOS process

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  • BiCMOS compatible JFET device and method of manufacturing same
  • BiCMOS compatible JFET device and method of manufacturing same
  • BiCMOS compatible JFET device and method of manufacturing same

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Embodiment Construction

[0025] reference figure 1 , Showing the structure of a vertical bipolar device obtained by a standard HBT (Heterojunction Bipolar Transistor) process, which provides a very high-performance transistor structure and uses more than one semiconductor material to construct, thereby utilizing Different band gaps of semiconductors used to form base, emitter and collector. The device shown includes a substrate 1 that also forms a heavily doped region of an n-type collector 2; and the collector 2 also includes a so-called drift region 3 that is lightly doped. The n-type emitter 4 includes a heavily doped region 5 (so-called "emitter outside" diffusion) and a weakly doped region 6 (or so-called n-type "emitter cap"). The respective doping concentrations of the emitter regions 5 and 6 can be, for example, 10 20 at / cm 3 And 10 18 at / cm 3 Of magnitude. An implanted extrinsic heavily doped p-type base region 7 is provided at the surface boundary of the semiconductor body, and the buried or in...

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Abstract

A BiCMOS compatible JFET device is disclosed comprising source and drain regions (17, 18) formed in the same manner as used to form emitter outdiffused or vertical bipolar devices , wherein the semiconductor layer forming the emitter cap in the bipolar device forms the channel (16) of the JFET device, and the material layer forming the intrinsic base region of the bipolar device (i.e., the base epi-stack layer) forms the intrinsic gate region (14) of the JFET device. As a result, the integration of JFET devices can be achieved in standard BiCMOS processes without any additional masking or other processing steps.

Description

Technical field [0001] The present invention generally relates to a BiCMOS process for manufacturing integrated circuits, and more specifically, to a JFET device compatible with a standard BiCMOS process and a manufacturing method thereof. Background technique [0002] Modern integrated circuits for high-performance RF applications generally rely on semiconductor processes including vertical bipolar junction transistors and traditional CMOS processes. [0003] Traditionally, in integrated circuit design, due to the high input impedance, improved cut-off frequency and lower noise figure of JFET (junction field effect transistor) compared to MOS (metal oxide semiconductor) field effect transistor, unipolar The JFET of the device serves as a good follower. On the other hand, because in a bipolar transistor, the transconductance is proportional to the emitter current, and in a JFET, the transconductance is proportional to the square root of the drain current, the JFET is not a good a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8248H01L27/098H01L27/06
CPCH01L27/098H01L27/0623H01L21/8248H01L27/06
Inventor 普拉巴特·阿加瓦尔扬·W·斯洛特布曼韦伯·D·范诺尔特
Owner NXP BV