Semiconductor packaging structure with intensification layer and encapsulation method thereof

Abstract

The invention discloses a semiconductor package structure with a strengthened layer, at least comprising a conducting wire support with a plurality of pins, a chip with the surface provided with a plurality of metal welding pads, a plurality of conductive convex blocks used to connect the metal welding pads of the chip and the pins of the conducting wire support, and a strengthened layer covering the surfaces of the pins and the conductive convex blocks. The material of the structure contains copper with the melting point higher than that of lead and tin, and is formed through electroplating.

Description

technical field [0001] The invention relates to a semiconductor packaging structure and a packaging method thereof, in particular to a good semiconductor packaging structure with a strengthening layer and packaging technology thereof. Background technique [0002] In recent years, portable terminal products, such as notebook computers, mobile phones, personal digital assistants (PDAs) and digital cameras have become a major mainstream. In order to achieve the ideal state of thinness, lightness and compactness, all technicians in the industry have racked their brains to go all out. However, taking mobile phones as an example, under the strong demand for lightness, lightness and compactness, chips are developed in conjunction with digitalization, high-speed processing, multi-function, and miniaturization of electronic devices. [0003] According to the above requirements, for the chip package, in addition to the miniaturization of the appearance size, it is also necessary to h...

AI Technical Summary

Problems solved by technology

[0007] However, in the semiconductor packaging method of the above prior art, there are still packaging technical problems that cannot be solved due to material characteristics, including the collapse of eutectic tin-lead bumps after reflow, and the reflow temperature of lead-free and high-lead bumps is too high The difference in thermal expansion coefficient between the chip and the copper nail frame is too large, causing problems such as bump cracking after packaging, which cannot effectively prevent the chip from being affected by moisture and heat, and provide a medium for the electrical connection between the chip and the external circuit. Thus losing the packaging purpose of the chip

It can be seen that the existing semiconductor packaging technology still has room for further improvement.

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