Device and a method and mask for forming a device

Abstract

A method of forming a semiconductor device includes patterning a layer stack to form single conductive lines and single landing pads. Patterning of the layer stack includes two lithographic exposures using a set of two different photomasks. The landing pads are arranged at on side of an array region defined by a plurality of conductive lines. A set of photomasks used in the method of forming a semiconductor device includes a first photomask including patterns corresponding to the conductive lines and a second photomask including patterns corresponding to the landing pads. A semiconductor device includes conductive lines and landing pads connected with corresponding ones of said conductive lines wherein the landing pads are arranged in a staggered fashion at one side of an array region defined by a plurality of conductive lines.

Description

technical field [0001] One embodiment of the present invention relates to a method of forming a semiconductor device and a mask used in the method. One embodiment of the invention relates to a semiconductor device. Background technique [0002] Semiconductor devices include arrays of wires in some layers of the device. The wires of such an array are typically arranged in parallel and are electrically insulated from each other laterally by a dielectric material. The lateral distance between two conductors and the width of the conductors add up to the pitch of the array of wires. The pitch is the dimension of a period of the periodic pattern arrangement. In order to reduce the necessary device area as much as possible, the lines succeed each other in a completely periodic manner. [0003] As an example, a semiconductor memory device includes an array of wires connecting certain portions of memory cells arranged in rows and columns and thus addressing these memory cells. H...

AI Technical Summary

Problems solved by technology

However, the lithography steps for simultaneous imaging of different ground rules (large areas of landing pads and small wires) are very difficult to implement because the lithography steps and the masks used must be optimized to image the smallest structure

Therefore, it is difficult to further shrink the word line width and pitch (word line width less than 70nm) using single-exposure lithography, and thus it is difficult to further shrink the memory device

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