Solder lug and manufacturing method thereof

A technology of solder bumps and manufacturing methods, which is applied in the manufacture of semiconductor/solid-state devices, electrical components, and electrical solid-state devices, etc. problem, to achieve the effect of good physical connection, easy miniaturization and portability, and volume reduction

Inactive Publication Date: 2007-12-19
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
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  • Application Information

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Problems solved by technology

[0009] Such as the solder bump manufacturing method described in the Chinese patent application No. "200310104780.6", using this method, the thickness of the Cu layer in the UBM layer 700 is about 5 microns; forming an overly thick Cu layer will not only lead to production time Prolonged, production efficiency reduces, and can cause the increase of the volume of the

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  • Solder lug and manufacturing method thereof
  • Solder lug and manufacturing method thereof
  • Solder lug and manufacturing method thereof

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[0051] In order to make the objectives, features, and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0052] Fig. 2 is a flowchart of the solder bump manufacturing process of the present invention; as shown in Fig. 2, the solder bump manufacturing process includes: pre-processing the wafer 100 including pads; sputtering on the pre-processed wafer 100 A UBM layer 700 is shot; a photoresist layer 600 is coated on the UBM layer 700, and the photoresist layer 600 is patterned to form a pattern area that exposes the local UBM layer 700; The protective layer 720 and the solder layer 720 are sequentially electroplated in the pattern area of ​​the agent layer 600 on the UBM layer 700; the photoresist layer 600 is removed, and the UBM layer 700 is patterned; and then solder bumps 800 are formed on the solder layer 720 , By which solder bump...

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Abstract

This inveention discloses a solder hump and its manufacturing method, which first of all coats a patttern photo resist layer on a wafer or UBM under salient points to form a figure area, in which, said UBM layer includes Cr/Cu, Cr/CrCu/Cu, Ti/Cu, TiW/Cu or Ta/Cu deposited layer by layer, then forms a Ni layer as the block layer in the figure, on the wafer or above the UBM layer and forms a Cu layer on the block layer as a welding layer and finally removes the photo resist layer on the un-figure region and etches the UBM layer covered by the un-figure region of the photo resist layer to form solder salient points on the welding layer to further realize connection of the wafer with outside by the welding way.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to the field of packaging of integrated circuit chips. Background technique [0002] As one of the three pillars of integrated circuit development, the packaging technology of integrated circuit chips not only directly affects the performance, reliability and cost of the integrated circuit itself, but also determines to a large extent the development of electronic whole systems to small, portable and multi-functional The process of functional direction development. Therefore, the industry pays more and more attention to the optimization process of integrated circuit chip packaging technology. [0003] For the current mainstream wafer level packaging (WLP), the preferred direction of improving the WLP process is to optimize the structure and manufacturing method of the solder bumps used to connect the chip with external circuits. [0004] FIG. 1 is a schematic diagra...

Claims

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Application Information

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IPC IPC(8): H01L23/485H01L21/60H01L21/28
CPCH01L24/11H01L2224/11H01L2224/13006H01L2924/01322H01L2924/14H01L2924/351H01L2924/00H01L2924/00012
Inventor 靳永刚王津洲蒋瑞华
Owner SEMICON MFG INT (SHANGHAI) CORP
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