Solder lug and manufacturing method thereof

Abstract

This inveention discloses a solder hump and its manufacturing method, which first of all coats a patttern photo resist layer on a wafer or UBM under salient points to form a figure area, in which, said UBM layer includes Cr / Cu, Cr / CrCu / Cu, Ti / Cu, TiW / Cu or Ta / Cu deposited layer by layer, then forms a Ni layer as the block layer in the figure, on the wafer or above the UBM layer and forms a Cu layer on the block layer as a welding layer and finally removes the photo resist layer on the un-figure region and etches the UBM layer covered by the un-figure region of the photo resist layer to form solder salient points on the welding layer to further realize connection of the wafer with outside by the welding way.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to the field of packaging of integrated circuit chips. Background technique [0002] As one of the three pillars of integrated circuit development, the packaging technology of integrated circuit chips not only directly affects the performance, reliability and cost of the integrated circuit itself, but also determines to a large extent the development of electronic whole systems to small, portable and multi-functional The process of functional direction development. Therefore, the industry pays more and more attention to the optimization process of integrated circuit chip packaging technology. [0003] For the current mainstream wafer level packaging (WLP), the preferred direction of improving the WLP process is to optimize the structure and manufacturing method of the solder bumps used to connect the chip with external circuits. [0004] FIG. 1 is a schematic diagra...

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Problems solved by technology

[0009] Such as the solder bump manufacturing method described in the Chinese patent application No. "200310104780.6", using this method, the thickness of the Cu layer in the UBM layer 700 is about 5 microns; forming an overly thick Cu layer will not only lead to production time Prolonged, production efficiency reduces, and can cause the increase of the volume of the integrated circuit chip of certain degree of integration and the increase of production cost; Simultaneously, in the UBM layer 700 of Al / NiV / Cu or Ti / NiV / Cu structure, NiV and Al Or the degree of bonding and matching of Ti is slightly poor, resulting in slightly poor stability of solder bumps, which in turn affects the reliability of integrated circuit chip packaging

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