Semiconductor device and its manufacturing method

A manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve the problems of thickening of the thickness of the semiconductor device, increase of the thickness of the semiconductor device, increase of the cost, etc., and the manufacturing process will not be Complicated effect

A manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve the problems of thickening of the thickness of the semiconductor device, increase of the thickness of the semiconductor device, increase of the cost, etc., and the manufacturing process will not be Complicated effect

CN101107710BInactive Publication Date: 2010-05-19PANASONIC CORP

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  • Semiconductor device and its manufacturing method
  • Semiconductor device and its manufacturing method
  • Semiconductor device and its manufacturing method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0092] figure 1 It is a sectional view of the semiconductor device showing the basic structure of the semiconductor device of the present invention.

[0093] As shown in the figure, the semiconductor device 150 is three-dimensionally mounted with two semiconductor chips 101 and 103 by flip-chip mounting.

[0094] That is, on the first semiconductor chip (lower semiconductor chip) 101, a bump electrode (a low-level electrode: hereinafter referred to as a first electrode) 102 formed by metal plating or the like is formed, and the first electrode 102 It is directly connected to a predetermined wiring pattern 106 formed on the substrate 105 . That is, the first semiconductor device is mounted on the main surface of the substrate 105 by flip-chip mounting.

[0095] Similarly, a tall electrode 104 (hereinafter referred to as a second electrode) is formed on the second semiconductor chip 103 , and the second electrode 104 is directly connected to a predetermined wiring pattern 106 ...

Embodiment approach 2

[0120] Figure 4 It is a cross-sectional view of a semiconductor device showing another example of the semiconductor device of the present invention (an example in which a first semiconductor chip and a second semiconductor chip are integrated). exist Figure 4 In , the same reference signs are attached to the parts common to the above-mentioned illustrations, and the description of the common parts will be omitted. This also applies to the illustrations below.

[0121] In the aforementioned embodiments, the two semiconductor chips are flip-chip mounted separately, but in this embodiment, the two semiconductor chips (101, 103) are first bonded, and then flip-chip mounted. The integrated semiconductor chips are mounted on the substrate 105 together.

[0122] That is, in the above-mentioned embodiments, the first semiconductor chip 101 and the second semiconductor chip 103 are not in contact or in a state of not being closely attached, but in this embodiment, the upper surfac...

Embodiment approach 3

[0134] Figure 5 It is a cross-sectional view of a semiconductor device showing another example of the semiconductor device of the present invention (an example in which the entire semiconductor device is sealed with resin).

[0135] In the present embodiment, the package structure is formed by sealing the bare chips (101, 103) with resin, thereby improving the water resistance or environment resistance of the semiconductor device. Such as Figure 5 As shown, the semiconductor device 158 of this embodiment is provided with a resin sealing body 109 for sealing the entire semiconductor device (other structures are the same as figure 1 same).

[0136] The sealing resin 109 is composed of epoxy resin, polyimide resin, acrylic resin, silicone resin, etc. with high heat resistance (glass transition temperature: 120-180°C), and preferably does not contain corrosion-inducing components such as halogen and organic phosphoric acid. . In addition, the curing temperature of the sealin...

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Abstract

The thickness and occupied area are reduced compared with conventional methods when semiconductor chips are three-dimensionally arranged, low-cost mounting is realized without using any other components, and the manufacturing process of the semiconductor device is simplified. A flip-chip mounting structure in which a first semiconductor chip (101) thinned by back-grinding and a substrate (105) aredirectly connected to a wiring pattern (106) through bump electrodes (102) is fabricated. For example, an electrode (104) higher than the sum of the thickness of the first semiconductor chip (101) and the electrode (102) is formed on a second semiconductor chip (103) and connected directly to the wiring pattern (106) on the substrate (105), thus providing a most-compact, three-dimensional semiconductor mounted device.

Description

technical field [0001] The present invention relates to a semiconductor device formed by three-dimensionally mounting a plurality of semiconductor chips on a common substrate by flip-chip mounting and a method of manufacturing the same. Background technique [0002] In order to achieve high density and miniaturization of semiconductor devices, semiconductor chips are often mounted on substrates by flip-chip mounting. Flip-chip mounting is a mounting method in which a bare semiconductor chip without a package structure is mounted in a flip-chip state on a wiring pattern of a substrate. [0003] Conventionally, there has been proposed a mounting structure in which another semiconductor chip is laminated on one flip-chip mounted semiconductor chip (or another semiconductor chip is three-dimensionally arranged on one semiconductor chip), so that the mounting area can be minimized. shrinkage (Patent Documents 1 to 3). [0004] In Patent Document 1, another semiconductor chip is...

Claims

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Application Information

Patent Timeline
19 May 2010
Publication
CN101107710B
IPC
H01L25/065; H01L25/07; H01L25/18
CPC
H01L2225/06517; H01L2225/06555; H01L25/0657; H01L2924/15151; H01L2224/73204; H01L2224/16225; H01L23/552; H01L2225/06582
Inventors
川端理仁; 冨士原义人