High voltage MOS transistor circuit simulated macro model

Abstract

The invention provides a high-voltage MOS transistor circuit simulation macro model, which belongs to the technical field of integrated circuit. The invention comprises a MOS transistor simulation model, an n channel JFET simulation model and a diode simulation model. The n channel JFET is connected in series in a drain electrode of the MOS transistor; the diode is connected in series between a source electrode and grid electrode of the MOS transistor. The invention has clear physic significance and its features can vary along the changes in parameter. Therefore, the invention can be supported and applied in all ordinary circuit simulator, EDA software and model software of the industry. Besides, the invention has the advantages of convenient and express extraction as well as accurate and fast simulation.

Description

technical field [0001] The invention belongs to the field of integrated circuits, in particular to a circuit simulation macro model of a high-voltage MOS transistor. Background technique [0002] In recent years, high-voltage MOS transistors have been widely used in circuits such as circuit output interfaces, LCD drivers, and power management chips. While improving the withstand voltage of the device, the cost is greatly reduced. The wide application of high-voltage MOS transistors makes more and more very large-scale integration (VLSI) designs and simulations require accurate high-voltage MOS transistor models. [0003] The structure of the high-voltage MOSFET is significantly different from that of the standard process low-voltage MOS transistor (LV MOSFET): the well depth, gate oxide thickness (Tox) and channel length of the high-voltage MOS transistor are larger than those of the low-voltage MOS transistor, most notably the high-voltage MOS transistor A lightly doped r...

AI Technical Summary

Problems solved by technology

As shown in Figure 2, a high-voltage transistor macro model currently used in the industry is mainly composed of a variable resistor connected in series to the drain D' and source S' of an ordinary SPICE transistor. However, the high-voltage transistor macro model The model has the following limitations, which prevent it from being widely used in the industry:

[0007] 1. Use a variable resistor whose resistance value changes with the terminal voltage to simulate the lightly doped drain diffusion region of the high-voltage MOS transistor, which only meets the simulation needs in terms of mathematical empirical formulas, and does not have physical meaning, making the model unable to have a full size Variable properties;

[0008] 2. The variable resistor whose resistance value changes with the terminal voltage cannot be supported and applied in a considerable number of circuit simulators, EDA software, and model software commonly used in the industry, and the extraction process is complicated and difficult, and its practicability cannot be guaranteed;

[0009] 3. It is necessary to add the temperature modulation coefficient of the variable resistor and the empirical formula to simulate the change of the characteristics of the high-voltage MOS transistor with temperature, which reduces the accuracy of the model

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