Interleaved three-dimensional on-chip differential inductors and transformers

Abstract

Interleaved three-dimensional (3D) on-chip differential inductors and transformers are disclosed. The interleaved 3D on-chip differential inductors and transformers make the best use of multiple metal layers in mainstream standard processes, such as CMOS, BiCMOS and SiGe technologies.

Description

[0001] Cross-references to related applications [0002] This application claims the Serial titled "Interleaved 3D On-Chip Differential Inductor and Transformer" filed Aug. 4, 2005 by Daquan Huang and Mau-Chung F. Chang Benefit of US Provisional Patent Application No. 60 / 705,868, the disclosure of which is incorporated herein by reference for all purposes permitted by statute. [0003] Statements related to federally sponsored research and development [0004] Development of this invention was made with government support under Award No. N66001-04-1-8934 awarded by the United States Navy. The US Government has certain rights in this invention. technical field [0005] This invention relates to inductors and transformers. In particular, the present invention relates to improved on-chip inductors and transformers and methods of manufacturing the same. Background technique [0006] On-chip inductors and transformers are key passive components in radio frequency / millimeter w...

AI Technical Summary

Problems solved by technology

In substrate-lossy silicon-based integrated circuits, it is especially important to fabricate on-chip inductors and transformers with as small a real area as possible, because the large area of ​​the inductor / transformer induces a large gap between the on-chip inductor / transformer and the substrate. Parasitic capacitance, which not only picks up unwanted noise from other parts of the circuit through the silicon substrate, but also severely limits the self-resonant frequency of on-chip inductors and transformers

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