A crystal wafer chip dimension encapsulation line and its making method

A wafer-level chip and size packaging technology, which is applied in the direction of circuits, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as short circuits between metals, and achieve the effect of reducing design distance, good application prospects, and significant social and economic benefits

Inactive Publication Date: 2008-03-26
CHINA WAFER LEVEL CSP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the consequence of doing this directly is that a short circuit between metals may occur when making the circuit

Method used

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  • A crystal wafer chip dimension encapsulation line and its making method
  • A crystal wafer chip dimension encapsulation line and its making method
  • A crystal wafer chip dimension encapsulation line and its making method

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Embodiment Construction

[0024] The packaging structure shown in Figure 1 is based on ShellOC technology and is a typical wafer-level chip-scale packaging. During production, firstly, the glass 5 with the cavity and the chip body 20 with the welding pad 15 are arranged and adhered, and then grinding, plasma etching, and cutting are performed sequentially to obtain a silicon inclined section or channel, and the part of the welding pad 15 is exposed. , making circuits on the bottom substrate 40, the circuits including leads and pads.

[0025] As shown in the wafer-level chip scale package circuit shown in FIG. 2 , the lead 35 is connected to the pad 15 and the pad 55 . The wires 35 connected to the pads 15 completely cover the pads 15 , and there is a certain distance between the pads 55 and the wires 35 .

[0026] FIG. 3 is a circuit pattern of a general wafer-level chip size package, and the circuit is generally composed of leads 35 and pads 55 . In order to prevent metal-to-metal short circuit, a c...

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Abstract

This invention relates to a wafer-size chip package circuit and its manufacturing method, in which, the circuit includes leads and pads, a compensation graph is set on a lead just opposite to an adjacent pad, or a compensation graph is set on the pad just opposite to an adjacent lead, when the circuit is processed, first of all a total metal layer is generated on the base matrix and coated with photoetch glue to form a necessary graph then to be made to a circuit with a method of depositing the metal, removing the photoresistance and the bottom metal.

Description

technical field [0001] The invention relates to the design and manufacture of circuit patterns, in particular to a wafer-level chip size package circuit and a manufacturing method thereof. Background technique [0002] With the increasing demand for the function and high integration of IC chips, and the requirement for the development of smaller electronic and optical devices, the semiconductor packaging industry is currently developing in the direction of wafer-level chip size packaging. [0003] Traditional packaging technologies such as wire bonding, tape automated bonding (TAB), and flip chip have their own shortcomings. In wire bonding and automated tape-and-load bonding, the size of the semiconductor package is much larger than the original size of the chip. The flip-chip package faces the electronic components down through the conductive solder bumps of the chip, so that the circuit side faces down, and is installed on the substrate / carrier for direct electrical conn...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/48H01L21/60
CPCH01L2924/14H01L24/05H01L2924/01327H01L29/0657H01L2924/10253H01L27/14618H01L24/13H01L27/14683H01L2224/0401
Inventor 虞国平俞国庆徐琴琴王文龙王蔚
Owner CHINA WAFER LEVEL CSP
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