Junction field effect tube and method of manufacturing the same

Abstract

A shallow channel region is selectively formed by ion implantation and diffusion. Since the channel region forms pn junctions with a p type semiconductor layer having a relatively low impurity concentration, a reduction of a junction capacitance leads to improvement in high-frequency characteristics. Moreover, since a gate region can also be shallowly formed by ion implantation, noise can be reduced by reduction in an internal resistance. Furthermore, a breakdown voltage and electrostatic breakdown characteristics can be improved by allowing the source and drain regions to penetrate the channel region.

Description

technical field [0001] The invention relates to a junction field effect transistor (FET) and a manufacturing method thereof, in particular to a junction field effect transistor with high withstand voltage and capable of improving high-frequency characteristics and noise characteristics and a manufacturing method thereof. Background technique [0002] In the existing junction field effect transistor, for example, an n-type trap region used as a channel region is provided on a p-type semiconductor substrate, an n+ type source region and a drain region are arranged in the n-type trap region, and an n+ type source region and a drain region are arranged in the source region. A gate region is formed between the drain region and the drain region (for example, refer to Patent Document 1). [0003] A conventional junction field effect transistor 200 will be described with reference to FIG. 9 . FIG. 9(A) is a plan view showing a conventional junction field effect transistor 200, and ...

AI Technical Summary

Problems solved by technology

[0019] However, in the conventional structure, when the impurity concentration of the channel region 24 is increased, there is a problem that the withstand voltage deteriorates.

Images