Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Flush type capacitance ultra-low inductance design

A technology of capacitors and capacitors, which is applied in the field of ultra-low parasitic inductance design, can solve the problems of reducing magnetism and reducing parasitic inductance of embedded capacitors, etc.

Active Publication Date: 2008-06-25
北京中科微投资管理有限责任公司
View PDF3 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although it is theoretically impossible to cancel the magnetic field in the medium to zero, this technology can greatly reduce the magnetic field in the interval, thereby reducing the parasitic inductance of the buried capacitor

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Flush type capacitance ultra-low inductance design
  • Flush type capacitance ultra-low inductance design
  • Flush type capacitance ultra-low inductance design

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0036] 1. The target impedance and upper limit frequency of the power supply network are determined by the technical parameters of the integrated circuit

[0037] Target impedance = power supply voltage × allowable fluctuation percentage / maximum transient current

[0038] Generally, the allowable fluctuation percentage is 5% to 10%, depending on the specific conditions of the system. The impedance of the system power supply network shall not be greater than this target impedance within the specified frequency range. The specified frequency range is generally from DC to the upper frequency limit. The upper limit frequency is generally defined as half the frequency of the rising edge of the signal. For example, a signal whose rising edge is 1 nanosecond has an upper limit frequency of 500MHz.

[0039] 2. Determine the reference capacitance

[0040] Only high frequency decoupling capacitors are estimated here. A reference capacitance value is determined by the upper freque...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to an ultralow parasitic inductance design of the discrete decoupling and embedding capacitor in a circuit board. Through holes or blind holes are densely arranged on an electrode, to reduce the parasitic inductance, to increase the working frequency of the embedded capacitor, and to improve the power integrity and the signal integrity of the circuit board. The lowest resonance frequency of the prior discrete embedding capacitor is genarally from hundreds of MHz to 2GHz, the so called medium frequency range. The prior design is hard to exceed 2GHz. With the working frequency of an electronic system is higher and higher and the speed is faster and faster, the corresponding improvement of the working frequency of a capacitor is required. The main factor restricting the working frequency of the embedded capacitor is the excessive parasitic inductance. However, because the restriction of the processing technology, the parasitic inductance is difficult to be reduced through the conventional method. Through using the multi-access method, The invention converts the serial distributed inductance into the parallel inductance, and thereby greatly reduces the parasitic inductance. Theoretically, the invention can reduce the parasitic inductance to zero.

Description

technical field [0001] The invention relates to the ultra-low parasitic inductance design of a discrete decoupling embedded capacitor in a circuit board. It is to densely arrange through holes or blind holes on the electrodes to reduce parasitic inductance, increase the operating frequency of embedded capacitors, and improve the power integrity and signal integrity of the circuit board. Background technique [0002] As the frequency and speed of integrated circuits increase, the operating voltage decreases, and noise suppression in the circuit power supply network in electronic systems becomes an extremely important factor affecting system performance. High-frequency and high-speed circuits mean fast response of the power supply, but due to the presence of inductance in the power supply network, it is impossible for the power supply to respond to the integrated circuit in a timely manner. For example, when a high-speed switching circuit is in a transient state, the power su...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/498H01L23/50H05K1/16
CPCH01L2224/16225
Inventor 万里兮
Owner 北京中科微投资管理有限责任公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products