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Semiconductor device with gate structure and method for fabricating the semiconductor device

A gate structure, semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as device characteristic degradation

Inactive Publication Date: 2008-07-02
SK HYNIX INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In this case, the threshold voltage of the sub-100nm gate structure may have a large variation, and therefore, the device characteristics may be degraded

Method used

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  • Semiconductor device with gate structure and method for fabricating the semiconductor device
  • Semiconductor device with gate structure and method for fabricating the semiconductor device
  • Semiconductor device with gate structure and method for fabricating the semiconductor device

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Embodiment Construction

[0028] Figure 3A ~ 3C The gate structures of PMOS devices each including a specific intermediate structure are illustrated. Figure 3A illustrated with a tungsten nitride (WN x ) single-layer gate structure. Figure 3B Illustrations that have included WSi x and WN x double-layer gate structure. Figure 3C Illustrated with titanium (Ti), titanium nitride (TiN x ) and WN x The three-layer gate structure. Here, x indicating the corresponding atomic ratio is a positive number. exist Figure 3A ~ 3C , each gate structure consists of a P + An electrode formed of polysilicon doped with type impurities and a metal electrode formed of W.

[0029] The gate structures of PMOS devices with different intermediate structures exhibit different characteristics. For intermediate structures containing a single layer, such as Figure 3A As shown, a Si-N dielectric layer may be formed on the interface of the polysilicon electrode. Therefore, the contact resistance of the gate struct...

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Abstract

A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-based electrode. An intermediate structure, which includes a titanium layer and a tungsten silicide layer, is formed over the polysilicon-based electrode. A metal electrode is formed over the intermediate structure.

Description

[0001] related application [0002] This application claims the benefit of Korean Patent Application Nos. 10-2006-0134368 and 10-2007-0041289 filed on December 27, 2006 and April 27, 2007, respectively, the entire contents of which are hereby incorporated by reference enter. technical field [0003] The present invention relates to a semiconductor device, and more particularly relates to a gate structure and a manufacturing method of the gate structure. Background technique [0004] Typically, as complementary metal-oxide-semiconductor (CMOS) devices become highly integrated, the gate pitch decreases. Certain limitations exist when the gate electrode and gate insulating layer are formed using conventional CMOS processes and materials. For this reason, it is expected to develop new materials that can replace conventional materials. [0005] In a conventional CMOS process, a polysilicon layer doped with N-type impurities is used to form gates of N-channel metal-oxide-semico...

Claims

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Application Information

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IPC IPC(8): H01L29/49H01L29/78H01L21/28H01L21/336
CPCH01L21/28061H01L21/324H01L21/823835H01L21/823842
Inventor 成敏圭梁洪善赵兴在金龙水林宽容
Owner SK HYNIX INC
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