Semiconductor device with gate structure and method for fabricating the semiconductor device

Abstract

A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-based electrode. An intermediate structure, which includes a titanium layer and a tungsten silicide layer, is formed over the polysilicon-based electrode. A metal electrode is formed over the intermediate structure.

Description

[0001] related application [0002] This application claims the benefit of Korean Patent Application Nos. 10-2006-0134368 and 10-2007-0041289 filed on December 27, 2006 and April 27, 2007, respectively, the entire contents of which are hereby incorporated by reference enter. technical field [0003] The present invention relates to a semiconductor device, and more particularly relates to a gate structure and a manufacturing method of the gate structure. Background technique [0004] Typically, as complementary metal-oxide-semiconductor (CMOS) devices become highly integrated, the gate pitch decreases. Certain limitations exist when the gate electrode and gate insulating layer are formed using conventional CMOS processes and materials. For this reason, it is expected to develop new materials that can replace conventional materials. [0005] In a conventional CMOS process, a polysilicon layer doped with N-type impurities is used to form gates of N-channel metal-oxide-semico...

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Problems solved by technology

In this case, the threshold voltage of the sub-100nm gate structure may have a large variation, and therefore, the device characteristics may be degraded

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