Microprocessor system for controlling or regulating at least partly security-critical processes

A microprocessor and security technology, applied in response to error generation, hardware redundancy for data error detection, redundant code for error detection, etc., can solve problems such as non-symmetrical design of memory

Inactive Publication Date: 2008-08-13
CONTINENTAL TEVES AG & CO OHG
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

The bus system associated with such a microprocessor system is similarly provided in duplicate, but for cost reasons the memory does not have a completely symmetrical design

Method used

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  • Microprocessor system for controlling or regulating at least partly security-critical processes

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Embodiment Construction

[0034] The microcontroller in Fig. 1 comprises two central processing units (CPUs) 1, 2, which operate in a clock-synchronized fashion. Both microcomputers execute the same program. Each unit has its own separate associated address and data bus. The CPU 1 has a full data storage 7 connected thereto, which is partially backed up using a test data storage 51 on the second bus. In addition, the microprocessor system contains a comparator 3 which takes the form of a hardware unit and is used to continuously compare the queued addresses and data on the two bus systems with each other. If there is a mismatch, an error signal is generated. For the purpose of simplifying the illustration, the figures do not show in more detail components that are typically found in a microprocessor system, such as input / output units, read-only memory, etc. These not shown components are essentially based on the redundant core microcontroller described in WO99 / 35543.

[0035] The test data storage ...

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PUM

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Abstract

A microprocessor system for controlling or regulating at least some safety-critical processes. A microprocessor system (50) for controlling or regulating at least some safety-critical processes, comprising: two central processing units (1, 2) integrated in a chip package; a first and a second bus system; at least one full memory (7) on a bus system; at least one test data storage device (51) on a second bus system having a reduced storage range compared to the full memory on the first bus system, and wherein storing test data linked to data in a memory (7) on a first bus system, the bus system comprising comparison and/or driver components allowing data exchange and/or data comparison between the two bus systems, and hardware The test data generator (4) is arranged at least on the second bus system, in which case at least part of the full memory on the first bus additionally uses the test data on the first bus and a further test data storage (5) Make a backup. The invention also relates to the use of the microprocessor system described above in a motor vehicle controller.

Description

technical field [0001] The invention relates to a microprocessor system according to claim 1 and its use in a motor vehicle controller. Background technique [0002] DE 195 29 434 A1 (P 7959) discloses a microprocessor system for safety-critical applications according to the preamble of claim 1 . For reasons of redundancy, such microprocessor systems contain two microprocessor cores of the same type (core redundancy), which execute the same program clock-synchronously and in parallel. The bus system associated with such a microprocessor system is similarly provided in duplicate, but for cost reasons the memory does not have a completely symmetrical design. It has been found that a high false recognition rate can be achieved if one of the two bus systems only stores test data in a test data storage device with a relatively low storage capacity. The test data is unambiguously associated with full data in full memory. Thus, each of the two cores makes all the data available ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10G06F11/16
Inventor W·法伊A·基施鲍姆A·特雷斯科夫
Owner CONTINENTAL TEVES AG & CO OHG
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