Scalable high speed wave front slope handler based on FPGA

A wavefront slope and processor technology, applied in optical components, optics, instruments, etc., can solve the problems of hardware circuit changes, expensive, complicated circuit board production, etc., to improve processing capabilities, improve processing capabilities, and achieve data throughput effect of ability

Inactive Publication Date: 2008-08-20
INST OF OPTICS & ELECTRONICS - CHINESE ACAD OF SCI
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Problems solved by technology

NSO's wavefront slope processor has powerful processing capabilities, but is expensive and complicated to make circuit boards
If a new su

Method used

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  • Scalable high speed wave front slope handler based on FPGA
  • Scalable high speed wave front slope handler based on FPGA
  • Scalable high speed wave front slope handler based on FPGA

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Embodiment Construction

[0024] As shown in FIG. 1 , the processor of the embodiment of the present invention has a total of 4 processing channels, which can complete the processing of the 4×4 sub-aperture arrangement.

[0025] As shown in FIG. 2 , the processing core module of the embodiment of the present invention is composed of a plurality of absolute differential pipelines with the same structure, and each pipeline forms a new pipeline structure under the synchronization of a synchronous clock. Image data and control instructions are transferred between absolute differential pipelines in a pipelined manner. Each absolute difference pipeline shares a part of the workload of sub-aperture absolute difference calculation, thereby improving the processing speed of the processing core.

[0026] As shown in Figure 3, each processing channel of the embodiment of the present invention is made of pixel address generation module, wave gate module, image ping-pong buffer module, operation core module, instru...

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Abstract

The invention is an upgradable high-speed wavefront slope processer based on FPGA which is composed of many channels, the channel number is equal to the sub-aperture inline number of one sub-aperture. Every channel is composed of pixel address generation module, wave gate module, image ping-pong buffer module, operation core module, instruction register module and addressing module, the whole processor is realized by single chip FPGA. The system upgrade goal is achieved by the repeated structure treatment channel in FPGA on the basis that the hardware circuit is not changed. Compared with the original system, the upgraded system delay does not change, the processing image resolution is high, and the sub-aperture amount is more.

Description

technical field [0001] The invention relates to a solar adaptive optics high-speed wave front processing system, in particular to an FPGA-based high-speed wave front slope processing machine that is easy to upgrade. Background technique [0002] In the solar adaptive optics system, it is necessary to perform high-speed real-time processing of extended target images such as sunspots and rice grain structures, and calculate their wavefront slopes to correct aberrations caused by atmospheric disturbances. According to the characteristics of the extended target image, the traditional centroid algorithm and other processing methods for point target images are no longer applicable, and are replaced by cross-correlation factor algorithm and absolute difference algorithm. The cross-correlation factor algorithm and the absolute difference algorithm have a huge amount of computation, and in order to achieve a better phase difference correction effect, the resolution of the CCD image s...

Claims

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Application Information

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IPC IPC(8): G02B26/06
Inventor 彭晓峰饶长辉李梅
Owner INST OF OPTICS & ELECTRONICS - CHINESE ACAD OF SCI
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