Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Data communication circuit with equalization control

一种数据信号、电路的技术,应用在信号的频率相关失真领域,能够解决消耗模拟电路面积、消耗功率和硅面积、均衡器调谐未对准等问题

Active Publication Date: 2008-10-08
NXP BV
View PDF0 Cites 21 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Here, data dependent errors cause equalizer tuning misalignment, since received power also depends on the sequence / order of transmitted bits
Second, ROM / RAM memory is required
[0012] Also, most prior art approaches require a lot of analog hardware like filters, peak detectors, amplifiers, etc., so these techniques consume a lot of power and silicon area
[0013] Therefore, prior art equalizer tuning algorithms are either limited to certain applications or require considerable power and area for consuming analog circuits

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Data communication circuit with equalization control
  • Data communication circuit with equalization control
  • Data communication circuit with equalization control

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0033] figure 1 A simplified block diagram of the receiver circuit for synchronous reception is shown. The circuit includes an adaptable equalizer 10 , a plurality of sampling amplifiers or samplers 12 , a digital post-processing circuit 14 , and a clock recovery circuit 16 . A circuit input 11 is coupled to a signal input of an equalizer 10 having an output coupled to each sampling amplifier 12 . The output of the sampling amplifier 12 is coupled to a digital post-processing circuit 14 . The digital post-processing circuit 14 has a first output coupled to the signal output 15 of the circuit and a second output coupled to the setting input of the equalizer 10 . Clock recovery circuit 16 has an output coupled to sampling amplifier 12 . The input of the clock recovery circuit may be coupled to the circuit input 11, or to an external clock source, or to a switch for selecting between the circuit input 11 and the external clock source. As an alternative to the clock recovery c...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

An adaptive equalizer comprises an adjustable equalizer circuit (10) that allows to enhance the frequency dependence of contents of the transmitted signals which suffer from losses in the connected transmission channel. A blind equalization tuning procedure is proposed that operates without knowledge about the characteristic of transmission channel. Phase positions of transitions in the equalized signal are detected through a transition phase detector (44). A digital post-processing circuit evaluates a measure for spread of the detected phase positions of transitions, accumulated over a plurality of the symbol periods. The digital post-processing circuit (14) controls the adjustable equalizer, setting the adjustable equalizer to a setting wherein the detected spread is minimized.

Description

technical field [0001] The present invention relates to data communication circuits. More specifically, the present invention relates to automatically adjusting channel equalization to compensate for frequency dependent distortion of signals transmitted over communication channels. Background technique [0002] The need to equalize signals in high-speed communications has been described in J. Liu et al., entitled "Equalization in High-Speed ​​Communication System", published in IEEE Circuits and Systems Magazine, pp. 4-17, 2004. [0003] A wired communication system conceptually consists of three distinct building blocks: a transmitter (TX), a channel (eg, cable or optical fiber), and a receiver (RX). Due to non-ideal channel characteristics such as limited bandwidth and crosstalk noise, the RX input signal is degraded such that data recovery on the receiver side stalls due to an unreasonable bit error rate (BER). This problem is exacerbated by the need to increase system ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H04L25/03
CPCH04L25/03885H04L25/0305H04L2025/03802H04L2027/0038
Inventor 弗雷德尔·杰弗斯格里特·W·邓百斯特恩吉姆·E·康德尔帕维尔·佩特科夫安德里斯·科伊尔曼
Owner NXP BV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products