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Power FET with low on-resistance using merged metal layers

A metal layer, high-power technology, applied in circuits, electrical components, semiconductor devices, etc., can solve difficult metal layers, passivation and other problems

Inactive Publication Date: 2011-04-20
MICREL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Third, it is difficult to fully passivate thick metal layers due to the high step size
Also, smaller vias cause a certain voltage drop due to their smaller cross-sectional area

Method used

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  • Power FET with low on-resistance using merged metal layers
  • Power FET with low on-resistance using merged metal layers
  • Power FET with low on-resistance using merged metal layers

Examples

Experimental program
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Embodiment Construction

[0023] FIG. 1 illustrates a simplified high power lateral FET 10 . In a real lateral FET there would be many more rows of alternating source and drain strips. FIG. 2 is a partial cross-section along line 2-2 in FIG. 1 . The invention is applicable to any type of FET, and the particular example of an n-channel lateral FET is not intended to be limiting. For example, the present invention is applicable to N-channel or P-channel cellular FETs and vertical FETs such as those described in U.S. Patent No. 5,355,008, assigned to the present assignee and incorporated by reference In this article.

[0024] An n-type source region 12 (FIG. 2) and an n-type drain region 14 are formed in the p-type layer 16 (or p-type barrel) of the silicon substrate. For p-channel FETs, the various conductivity types can be reversed. A gate oxide is grown on the channel region and a doped polysilicon gate 18 is formed. Gate 18 is connected to a voltage source (not shown) to switch the transistor on ...

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Abstract

The invention relates to a power FET with low on-resistance using merged metal layers. In one embodiment, relatively thin but wide metal bus strips overlying a high power FET are formed to conduct current to the source and drain narrow metal strips. A passivation layer is formed over the surface of the FET, and the passivation layer is etched to expose almost the entire top surface of the bus strips. A copper seed layer is then formed over the surface of the wafer, and a mask is formed to expose only the seed layer over the bus strips. The seed layer over the bus strips is then copper or goldelectroplated to deposit a very thick metal layer, which effectively merges with the underlaying metal layer, to reduce on-resistance. The plating metal does not need to be passivated due to its thickness and wide line / space. Other techniques may also be used for depositing a thick metal over the exposed bus strips.

Description

technical field [0001] The present invention relates to high power field effect transistors (FETs), and in particular, to a technique for using additional metal layers to reduce the on-resistance of such FETs. Background technique [0002] One type of conventional high power FET is formed by forming long rows of alternating source and drain regions separated by a channel region. A gate overlies the channel region. The gate width is therefore very large to form a high current FET. The source and drain regions are of the same conductivity type, and the threshold voltage on the gate forms a conductive channel between the source and drain to conduct current. This transistor is a lateral FET. Narrow metal strips contact and interconnect the source regions, and other metal strips contact and interconnect the drain regions. [0003] Another type of high power lateral FET forms source and drain region units separated by a channel with the gate overlying the channel. Each pair o...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L21/336H01L29/417H01L23/482H01L21/28
CPCH01L23/4824H01L2924/0002H01L2924/00
Inventor 马丁·奥特尔里夏德·多兰
Owner MICREL