Method and system for eliminating reaction ion auto-bias
A technology of reactive ion etching and ion etching, applied in electrical components, circuits, semiconductor/solid-state device manufacturing, etc., can solve the problems of semiconductor lattice damage, performance deterioration, device leakage increase, etc., and achieve the effect of reducing damage
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0021] Such as figure 2 As shown, in the embodiment of the present invention, an LC resonant circuit composed of an inductance coil L and a capacitor C is connected in parallel between the two electrodes (cathode and anode) of the RIE reaction chamber. Wherein, the inductance coil L and the capacitor C are connected in parallel, and the resonant frequency of the LC resonant circuit is the same as the frequency of the radio frequency (RF) power supply of the RIE reaction chamber. Through the inductance coil L in the LC resonant circuit, the DC self-bias voltage between the two electrodes of the RIE reaction chamber is short-circuited, so that the original DC self-bias voltage can be reduced to zero or close to zero; in addition, due to the parallel LC resonant circuit Resonance occurs at the frequency point of the RF power supply, and the impedance of the LC resonance circuit is the highest at this frequency point. Therefore, the introduction of the LC resonance circuit will n...
Embodiment 2
[0023] In practical applications, in order to maintain the advantages of fast RIE etching rate and overcome the disadvantage that RIE etching is easy to cause serious damage to the semiconductor lattice, during the etching process of RIE, the semiconductor lattice can be taken first. RIE fast etching with self-bias voltage, and then connect an LC resonant circuit in parallel between the two electrodes of the RIE reaction chamber, so that it can perform low-damage RIE etching without self-bias voltage, so as to reduce the surface lattice of semiconductor devices damage, improving device performance and yield, such as image 3 shown. The method adopted to realize the above-mentioned technical solution is: the LC resonant circuit is connected in parallel between the two electrodes of the RIE reaction chamber through a switch K; In the off state, the LC resonant circuit is not connected; when the semiconductor lattice is etched by RIE without self-bias voltage, the switch K is in...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 