Nonvolatile memory structure and array thereof

Abstract

The invention relates to the technical field of non-volatile memories and discloses a non-volatile memory structure which comprises a substrate, multiple stack patterns and multiple stress patterns. The stack patterns are arranged on the substrate, and each stack pattern comprises a charge storage structure and a gate from bottom to top; wherein, the charge storage structure at least comprises a charge storage layer. The stress patterns are respectively arranged on the substrate between two adjacent stack patterns. The invention also discloses a non-volatile memory array. The non-volatile memory structure and non-volatile memory array effectively simplify the manufacturing process and improve the production efficiency of products. Furthermore, the non-volatile memory structure and the array thereof have better electrical property.

Description

technical field [0001] The invention relates to the technical field of nonvolatile memory, in particular to a nonvolatile memory structure and an array thereof. Background technique [0002] The electrically erasable programmable read only memory (electrically erasableprogrammable read only memory, EEPROM) in the non-volatile memory has the functions of storing, reading, erasing and writing data multiple times, and the stored data is It has the advantage of not disappearing later, so it has become a memory element widely used in personal computers and electronic equipment. [0003] A typical EEPROM uses doped polysilicon to make a floating gate (also known as a floating gate) and a control gate. When the memory is programmed, electrons injected into the floating gate are uniformly distributed throughout the polysilicon floating gate layer. [0004] In addition, there is also an EEPROM commonly used at present, which uses a charge trapping layer to replace the polysilicon f...

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Problems solved by technology

However, the above commonly used memories have disadvantages such as low read current, poor transconductance (GM), slow programming speed, and short data storage time in terms of electrical performance.

[0006] In addition, the silicon oxide isolation pattern located above the doped region needs to use complex manufacturing methods such as lift-off method, which will reduce the production efficiency and yield of products.

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