High-efficiency simulating and verifying device for large test and excitation

Abstract

The device is used for processor chip level verification based on reference modelling verification to improve the simulation and verification efficiency of large test and excitation (operating instruction number is more than 106, such as large pseudo random excitation, operating system and typical user task). The device combines advantages of fast operating speed and high reliability of reference model and precise time sequence and easy error debugging of register transfer level (short for RTL) model structure, uses save-restore principle, takes visible status of processor software as content of save-restore to realize fast and agile status switch and continue operation between reference model and RTL model and make user able to focus on verifying hotspot in simulation and verification of large test and excitation. So it saves unnecessary initial running or intermediate running processes, well solves the problems that simulation time for large test and excitation is too long due to the slow operating speed of RTL model and testing and debugging waste time and energy. Synchronously, the device also provides correctness confirming mechanism for the simulation result of large test and excitation.

Description

technical field [0001] The invention is a device for improving the efficiency of large-scale test stimulation simulation verification. Background technique [0002] In processor verification, simulation verification of large-scale test stimuli (such as large-scale pseudo-random stimuli, operating systems, and typical user topics, etc.) is indispensable. It can fully discover design errors and ensure the correctness of processor software and hardware interfaces. valid verification. However, such incentives are usually very large, the number of running instructions is on the order of millions or even billions, and the number of simulation ticks is also on the order of magnitude. Microprocessor design generally has considerable complexity, and it must cooperate with peripheral design (such as memory controller, network interface and peripheral controller, etc.) to carry out chip-level simulation verification. Under the current hardware and software resource conditions, the RT...

AI Technical Summary

Problems solved by technology

Microprocessor designs generally have considerable complexity, and must cooperate with peripheral designs (such as memory controllers, network interfaces, and peripheral controllers, etc.) to perform chip-level simulation verification

Under the current hardware and software resource conditions, the RTL-level model simulation running speed of the processor is usually very limited, generally within 10 3 Beats per second, the simulation speed of some high-performance microprocessors and complex system environments can only reach a few beats per second

The speed of RTL-level model simulation verification is far from meeting the needs of large-scale test stimulus test simulation. An efficient and useful device is needed to solve this problem. Continuity and consistency of large test stimuli running in simulation must be ensured

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