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Production method for thin-film transistor array substrate

A thin-film transistor and array substrate technology, which is applied in the manufacturing field of thin-film transistor array substrates, can solve problems such as high manufacturing cost, cumbersome 9-pass photomask process, and difficult yield control.

Inactive Publication Date: 2010-06-16
CHUNGHWA PICTURE TUBES LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, compared with the 5-step photomask process of the general amorphous silicon thin film transistor (a-Si TFT) array substrate, the 9-step photomask process of the low-temperature polysilicon thin film transistor array substrate is extremely cumbersome.
Therefore, the existing low-temperature polysilicon thin film transistor array substrate technology is not only difficult to increase the panel size, but also difficult to control the yield rate, which in turn causes the problem of high manufacturing costs

Method used

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  • Production method for thin-film transistor array substrate
  • Production method for thin-film transistor array substrate
  • Production method for thin-film transistor array substrate

Examples

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Effect test

no. 1 example

[0035] Figure 3A to Figure 3G It is a schematic diagram of the manufacturing process of a thin film transistor array substrate according to the first embodiment of the present invention. Please refer to Figure 3A As shown, firstly, a substrate 310 is provided, and the substrate 310 has a peripheral area 310a and an array area 310b. In addition, the substrate 310 can be a glass substrate, a quartz substrate or a plastic substrate. Then, a polysilicon layer 330 is formed on the substrate 310 .

[0036] In more detail, the step of forming the polysilicon layer 330 is, for example, first forming an amorphous silicon layer (not shown) on the substrate 310, and the method of forming the amorphous silicon layer is, for example, chemical vapor deposition (chemical vapor deposition, CVD) process or ion growth chemical vapor deposition (plasma enhanced CVD, PECVD) process. Then, a laser annealing process is performed on the amorphous silicon layer to transform the amorphous silico...

no. 2 example

[0052] Figure 4A to Figure 4E It is a schematic diagram of the manufacturing process of a thin film transistor array substrate according to the second embodiment of the present invention. Please refer to Figure 4A As shown, first, a substrate 310 is provided, and the substrate 310 has a peripheral region 310a and an array region 310b, and a plurality of first polysilicon islands 330a and a plurality of second polysilicon islands are formed on the substrate 310 330b and a plurality of third polysilicon islands 330c. Wherein, the first polysilicon island 330a and the second polysilicon island 330b are located on the peripheral area 310a, and the third polysilicon island 330c is located on the array area 310b. Next, a second patterned photoresist layer 420b is formed on the first, second and third polysilicon islands 330a, 330b, 330c by using a second half-tone photomask 410b, and the second patterned photoresist layer The resistive layer 420b covers the first polysilicon is...

no. 3 example

[0060] Figure 5A to Figure 5F It is a schematic diagram of the manufacturing process of a thin film transistor array substrate according to the third embodiment of the present invention. Please refer to Figure 5AAs shown, first, a substrate 310 is provided, and the substrate 310 has a peripheral region 310a and an array region 310b, and a plurality of first polysilicon islands 330a and a plurality of second polysilicon islands are formed on the substrate 310 330b and a plurality of third polysilicon islands 330c. Wherein, the first polysilicon island 330a and the second polysilicon island 330b are located on the peripheral area 310a, and the third polysilicon island 330c is located on the array area 310b. Similarly, a buffer layer 320 may be formed on the substrate 310 first, and then the first, second and third polysilicon islands 330a, 330b, 330c are formed. The methods and materials for forming the buffer layer 320 , the first, second and third polysilicon islands 330 ...

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Abstract

The invention discloses a thin-film transistor array substrate manufacture method comprising: forming a pattern light blockage layer on a first polycrystalline silicon island, a second polycrystallinesilicon island and a third polycrystalline silicon island by using a half mode photomask; performing a second ion injection process and forming a second source electrode / drain in the second polycrystalline silicon island and a third source electrode / drain in the third polycrystalline silicon island, wherein a second channel region is between the second source / drain and a third channel region isbetween the third source / drain; removing the pattern light blockage layers above the second polycrystalline silicon island and the third polycrystalline silicon island; performing the channel region doping process so as to inject ions in the second polycrystalline silicon island and the third polycrystalline silicon island; removing the pattern light blockage layers.

Description

[0001] This application is a divisional application of the invention patent application with the application number "200610125671.6" and the invention title "Manufacturing Method of Thin Film Transistor Array Substrate" submitted by the applicant on August 25, 2006. technical field [0002] The invention relates to a method for manufacturing an active element array substrate, and in particular to a method for manufacturing a thin film transistor array substrate. Background technique [0003] The low temperature poly-silicon thin film transistor (LTPS TFT) overcomes the problem of electron mobility, and also provides complementary circuit technology. Therefore, low-temperature polysilicon thin film transistors have great advantages in device miniaturization, panel aperture ratio, picture quality and resolution. In addition, the current design of low-temperature polysilicon thin film transistors not only has the characteristics of integrating the driving circuit on the glass, ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/84
Inventor 萧富元温佑良
Owner CHUNGHWA PICTURE TUBES LTD