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Power management method and related chipset thereof

A technology of power management and power management module, applied in data processing power supply, electrical digital data processing, digital data processing components and other directions, can solve the problems of phase-locked loop power consumption, inability to effectively reduce power consumption, etc., to reduce power consumption Effect

Active Publication Date: 2011-02-16
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In other words, when the computer system is operating normally, the power loss cannot be effectively reduced due to the power consumption of the phase-locked loop

Method used

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  • Power management method and related chipset thereof
  • Power management method and related chipset thereof
  • Power management method and related chipset thereof

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Experimental program
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Embodiment Construction

[0018] In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are listed below and described in detail in conjunction with the accompanying drawings.

[0019] figure 2 A computer system 200 is shown in accordance with an embodiment of the invention. Wherein, the computer system 200 can be operated in a working state (such as ACPI state S0) and multiple power-saving states (such as ACPI states S1-S5), only when operating in the working state, the computer system 200 is in the state of normal operation, and the rest The power-saving state is in sleep state. like figure 2 As shown, the computer system 200 includes at least a processing unit 210 , a clock generator 220 and a chipset 230 . The clock generator 220 is used for generating a first clock signal. The chipset 230 is coupled to the processing unit 210 and the clock generator 220 , wherein the chipset 230 includes a phase-locked loop 23...

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PUM

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Abstract

The invention provides a power management method and a related chipset thereof which are applicable to a computer system, wherein, the computer system comprises a processing unit, a power management module and a phase lock loop circuit; and the power management module is coupled with a plurality of peripheral modules, and the computer system and the processing unit can be respectively operated inan operating mode and a plurality of power-saving modes. The power management method comprises the following steps: state of the peripheral modules is detected so as to judge whether to meet a special condition when the computer system is operated in the operating mode and the processing unit is in the minimum power consumption power-saving mode among the power-saving modes; and the processing unit is caused to be in a control state so as to control operation of the phase lock loop circuit according to a set control state when the state of the peripheral modules meets the special condition. The power management method can reduce power consumption of the whole computer system more effectively and achieve the purpose of power control.

Description

technical field [0001] The present invention relates to a power management method and its related management device and chipset, and in particular to a power management method for the processor power state of an Advanced Configuration and Power Interface (ACPI), which is used to control Operation of a phase locked loop in a computer system. Background technique [0002] In order to provide power management, current computer systems such as personal computers or portable computers use Advanced Configuration and Power Interface (ACPI for short) to effectively monitor and distribute the supplied energy to the computer systems. each element. ACPI defines five states, for example: S0, S1, S3, S4, and S5. However, only the state S0 is a state in which the computer system operates normally, and the rest of the states S1 to S5 are in a sleep state. In addition, ACPI also defines the power-saving state of the CPU in state S0. [0003] figure 1 Defines CPU power state diagrams fo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/32
CPCG06F1/3237Y02B60/1221Y02B60/32G06F1/3215Y02D10/00Y02D30/50
Inventor 秦双双黄正维
Owner VIA TECH INC