Electrical level translation circuit

Abstract

The invention discloses an electrical level translation circuit, which comprises an electrical level translator, an inverter, a first switch circuit and a second switch circuit. The electrical level translator comprises a first transistor, a second transistor, a third transistor and a fourth transistor. The inverter is used for receiving an input signal and accordingly generates an inverse input signal. The first transistor and the second transistor are controlled by the input signal and an output signal respectively to output an inverse output signal. While the third transistor and the fourth transistor are controlled by the inverse input signal and the inverse output signal respectively to output the output signal. The first switch circuit is coupled to the electrical level translator and turns off the fourth transistor when the third transistor is turned on. While the second switch circuit is coupled to the electrical level translator and turns off the second transistor when the first transistor is turned on.

Description

technical field [0001] The present invention relates to a level shifter circuit, and in particular to a voltage shifter circuit which improves switching speed and reduces short-circuit current. Background technique [0002] Please refer to figure 1 , which shows a circuit diagram of a conventional level shifting circuit. The conventional level shifting circuit 10 includes a level shifter 110 and an inverter 120 . The inverter 120 is used to receive the input signal IN and invert it to generate an inverted input signal IN' and output it to the level shifter 110 . Wherein, the inverter 120 includes a transistor P3 and a transistor N3, and the transistor P3 and the transistor N3 are respectively a P-type metal-oxide-semiconductor transistor (PMOS) and an N-type metal-oxide-semiconductor transistor (NMOS). The control terminal of the transistor P3 is coupled to the control terminals of the transistor N3 and the transistor N1, and the second terminal of the transistor P3 is co...

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Problems solved by technology

[0010] In addition, since the transistor N2 and the transistor P2 are both in the conduction state, the output signal OUT will be at the power supply voltage V DD and the power supply voltage Vss pull phenomenon

[0011] In this way, not only the traditional level conversion circuit 10 is too slow, but also the short-circuit current I DS1 It will also cause unnecessary power consumption (PowerConsumption) of the level conversion circuit 10

In addition, when the power supply voltage Vcc is turned off and the power supply voltage VDD is still on, since the output signal OUT and the inverted output signal OUT' are floating, a large leakage current will be induced.

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