Multi-chip stacking method for halving routing procedure and structure thereof

Abstract

The invention discloses a multi-chip stacking method for halving routing procedure, comprising the following steps: firstly, providing a support plate having two or more finger joints and arranging at least one first chip on the support plate; then, routing to form two or more bonding wires to connect a first electrode of the first chip to the finger joints; arranging at least one second chip on the first chip face to face, and meanwhile, joining the second electrode of the second chip to one end of the bonding wires on the first electrodes, so that the second chip is electrically connected to the support plate through the bonding wires. The invention also discloses a multi-chip stacking structure for halving routing procedure. Therefore, the invention can shorten the procedure period and save cost, ensures that the bonding wires are located at the routing end on the chip and connected to the first electrode, and avoids line disconnection and line breasting.

Description

technical field [0001] The present invention relates to a multi-chip stacking technology applicable to semiconductor devices, in particular to a multi-chip stacking method and structure which halves the wiring process. Background technique [0002] In order to improve the performance and capacity of a single semiconductor device to meet the trend of miniaturization, large capacity and high speed of electronic products, generally speaking, multiple chips are stacked on the carrier board to save space. However, the number of wire bonding electrical connections in the process corresponds to the number of chip stacks. When the number of chip stacks increases, the number of wire bonding electrical connections also increases, making the process complicated and prone to wire punching problems. [0003] see figure 1 shown and with reference to figure 2 , a known multi-chip stacking method includes the following steps: Step 1, providing a carrier board; Step 2, setting the chips f...

AI Technical Summary

Problems solved by technology

[0004] Since the first chip 120 and the second chip 140 are respectively connected to the carrier 110 by dedicated first bonding wires 131 and second bonding wires 132, In the process, it needs to go through two wire bonding, corresponding to the number of chip stacks, to achieve the electrical interconnection between the first chip 120, the second chip 140 and the carrier 110, so the multi-channel wire bonding process cannot be omitted

Moreover, too many welding wires in the crowded sealing space are prone to the problem of punching wires

In addition, it is known that these bonding wires 131 and 132 are all bonded in the forward direction, so as to avoid the phenomenon of false soldering or empty soldering on the joints on the chip, but the maximum arc height of these bonding wires 131 is above the first chip 120. superior

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