Semiconductor device interconnected structure and manufacturing method thereof

Abstract

The invention relates to a manufacturing method for a semiconductor device interconnected structure. The manufacturing method comprises the steps of providing a semiconductor device interconnected structure matrix provided with interlevel dielectrics, and forming a compound medium layer on the semiconductor device interconnected structure matrix. The compound medium layer comprises a bottom cover layer arranged on the bottom of the compound medium layer, a sandwich layer arranged in a sandwich layer groove, and a top cover layer arranged on the top of the compound medium layer, wherein the sandwich layer groove is arranged in the bottom cover layer. The invention also provides the semiconductor device interconnected structure. The invention adopts the compound medium layer as the top cover layer, improves the mechanical strength of the whole interconnected structure and ensures that a chip is not easy to break in the use process. The material with higher thermal conduction in the top cover layer can easily and timely dissipate the heat generated in the working process of the chip, ensures that the chip cannot be burned down due to overhigh temperature and ensures the working efficiency and the stability of the chip.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to an interconnection structure of a semiconductor device and a manufacturing method thereof. Background technique [0002] One of the challenges encountered in the field of integrated circuit design and manufacturing today is how to reduce the RC delay (Resistive Capacitive delay) of signal transmission. For this, one method that has been adopted in the prior art is to replace aluminum interconnection lines with copper interconnection lines , to reduce the series resistance of wires; another method is to reduce the parasitic capacitance between metal wires, which can be achieved by constructing porous (Porous) low dielectric constant (Low k) materials or air gaps in the dielectric layer between metal wires (Air Gap) to achieve. [0003] In addition, when the integrated circuit is working, due to the flow of current in the circuit, and the wire has a certain imp...

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Problems solved by technology

[0006] The existing method for making the interconnection structure of semiconductor devices uses a general dielectric layer to be formed on the substrate of the interconnection structure of semiconductor devices, to seal the porous interlayer dielectric in the interlayer dielectric, or to seal the air gap opening in the interlayer dielectric so that An air gap is formed in the interlayer dielectric, which can reduce the parasitic capacitance between the metal wires of the semiconductor device interconnection structure to reduce the RC delay of signal transmission, but at the same time, due to the porous structure or air gap in the interlayer dielectric, it will also Reduce the mechanical strength of the entire interconnection structure, making the chip easy to break during use, the electrical connection between the metal wires of the interconnection structure is lost, and the circuit cannot work normally; and the porous structure or air gap usually also reduces the overall interconnection. The thermal conductivity of the structure prevents the heat generated by the circuit in the chip from dissipating quickly, which may cause the inside of the chip to be burned due to excessive temperature, thereby affecting the working efficiency and stability of the entire chip

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