Defect test structure of semiconductor device, defect test method and defect test structure of before-metal medium layer

Abstract

The invention discloses a defect test structure of a semiconductor device, a defect test method and a defect test structure of a before-metal medium layer, wherein the defect test structure of the semiconductor device comprises a semiconductor substrate, n grooves which are arranged on the semiconductor substrate and parallel to one another, and a medium layer filled in the grooves; n is a naturalnumber which is more than or equal to 3; and in a top view of the defect test structure, an inclination angle between a connecting line connecting one end of all grooves and a vertical line of the grooves is beta. Correspondingly, the invention also discloses the defect test method of the semiconductor device and the defect test structure of the before-metal medium layer. The defect test structure and the defect test method have the advantages of saving test steps, improving production efficiency, and facilitating cost reduction.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a defect testing structure of a semiconductor device, a defect testing method and a defect testing structure of a pre-metal dielectric layer. Background technique [0002] With the increasing demand for high integration and high performance of ultra-large-scale integrated circuits, semiconductor technology is developing towards technology nodes with 65nm or even smaller feature sizes. With the continuous scaling down of device sizes, gap filling capabilities of thin film deposition are also required (Gap-fill ability) has been further improved. For example, the High Density Plasma PhosphoSilicate Grass (HDPPSG) process used to form the pre-metal dielectric layer (Pre-Metal Dielectric, PMD) has been proven to be used in the manufacture of logic circuits at the 90nm technology node. The pre-metal dielectric layer filled in the window between the gate structures...

AI Technical Summary

Problems solved by technology

figure 2 for figure 1 The enlarged cross-sectional schematic diagram along the D-D direction, the gate 30 (see figure 1 ) between the pre-metal dielectric layer 50 has a strip-shaped void defect 70, but in the actual production process, the pre-metal dielectric layer 50 is formed first, and then the contact hole 80 and the contact hole 90 are etched, respectively in the contact hole 80 and the contact hole. The hole 90 is filled with metal to form the metal contact plugs A1 and A2, and the void defect 70 connects the contact hole 80 with the contact hole 90. After filling the metal, it is likely to cause a short circuit of the device.

[0007] However, the problem is that the use of the above-mentioned defect testing structure requires the use of FIB technology to cut the substrate multiple times, and the FIB technology itself is not only complicated but also expensive. In this way, the efficiency will be reduced in mass production and the production capacity of integrated circuit manufacturing will be affected. promote

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