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Semiconductor structure with stress area

A semiconductor and stress region technology, applied in semiconductor devices, transistors, electric solid devices, etc., can solve the problem of limited stress effect and achieve the effect of improving carrier mobility

Active Publication Date: 2011-08-31
EON SILICON SOLUTION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, if the stress layer is too thick, it will affect the difficulty of caulking afterwards
If it is too thin, the stress effect produced will be limited

Method used

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  • Semiconductor structure with stress area
  • Semiconductor structure with stress area
  • Semiconductor structure with stress area

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0027] refer to figure 2 , using an existing deposition technique, e.g. source gas containing NH 3 and SiH 4 An oxide layer 210 is deposited here by chemical vapor deposition (CVD), rapid thermal chemical vapor deposition (RTCVD), atomic layer deposition (atomic layer deposition, ALD). The thickness of the oxide layer 210 is between to In this example is The sum of the deposited thicknesses of the oxide layers 110 and 210 next to 106 b and 106 d is at least greater than half of the width d of the region 107 to seal the region 107 . Then the oxide layer 210 is etched into a plurality of oxide spacers (Oxide spacers) 310a-310d (see image 3 ), and the oxide layers 110 and 210 located on 106d are completely etched away (see image 3 ).

[0028] refer to Figure 4, the second oxide layer 110 forms a first, second, third and fourth L-shaped spacers (L-shape) 402, 404, 406, 408 (wherein, the first and third L-shaped spacers 402 and 406 Inverted L-shaped), said L-shaped...

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Abstract

The invention relates to a semiconductor structure with a stress area, which comprises a substrate, the stress area, and a position barrier plug, wherein the substrate is provided with a first element area and a second element area; the stress area is positioned in the first element area and the second element area and comprises a first part and a second part respectively in the first element area and the second element area, and the stress generated by the first part and the second part is different; and the position barrier plug separates the first element area and the second element area. The stress generated by the stress area improves field-effect mobility so as to improve the read current; therefore, lower read voltage can be used to achieve the originally required read current so as to reduce the possibility of the stress-induced leakage current (SILC) to improve the persistence of data in the semiconductor storage structure.

Description

technical field [0001] The present invention relates to a metal-oxide-semiconductor (MOS) structure, and more particularly to a semiconductor structure with a stress region. Background technique [0002] With the advancement of technology, the process technology of flash memory has also entered the nanometer era. In order to accelerate the operating speed of the device, increase the integration of the device, and reduce the operating voltage of the device, etc., the channel length and oxide layer of the device gate Thickness shrinkage is an inevitable trend. The element gate line width has changed from the previous micron (10 -6 meters) down to the current nanometer (10 -9 Meters), however, with the miniaturization of components, it also brings many problems, such as: the shortening of the voltage-induced leakage current (stree-induced leakage current, SILC) and the gate line width will make the short channel effect (Short Channel Effect) It is getting more and more serio...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/088H01L27/12
Inventor 陈宏玮吴怡德
Owner EON SILICON SOLUTION