Structure taking part of metal grid as grid medium etching blocking layer with high dielectric constant and integration method

Abstract

The invention relates to a structure taking part of a metal grid as a grid medium etching blocking layer with high dielectric constant and an integration method, belonging to the technical field of semiconductor chips. The method comprises the following steps: taking part of the metal grid as the etching blocking layer for etching a high-K material when etching the high-K material; after integrating, enabling the threshold voltage of NMOS and PMOS to conform to requirements by simplified steps. The invention has the advantages of overcoming the nail pricking effect of the fermi energy level ofa PMOS grid, solving the problem that the traditional technique damages a high-K medium when removing photoengraving glue, and simplifying the integration complexity of a high-K metal grid greatly.

Description

technical field [0001] The invention belongs to the technical field of semiconductor chips, and in particular relates to a structure and an integration method of a high dielectric constant (high K) gate dielectric and a metal gate. Background technique [0002] In recent years, microelectronics technology with silicon integrated circuits as the core has developed rapidly. The development of integrated circuit chips basically follows Moore's law, that is, the integration level of semiconductor chips doubles every 18 months. However, as the integration of semiconductor chips continues to increase, the channel length of MOS transistors is also continuously shortened. When the channel length of MOS transistors becomes very short, the short channel effect will degrade the performance of the semiconductor chip, or even fail to operate normally. Work. [0003] In order to overcome the adverse effects caused by short channel effects (such as threshold voltage drop, etc.), MOS trans...

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Problems solved by technology

[0005] The object of the present invention is to provide a semiconductor chip integration method to improve the problem of damage to the high-K gate dielectric material when removing the photoresist, overcome the Fermi level pinning effect of the PMOS gate, and simplify the high-K metal gate The complexity of the integration, and provide the structure of the etch barrier layer of the corresponding high-K gate dielectric layer

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