Method for detecting random defects of silicon gate of CMOS process

Abstract

The invention discloses a method for detecting random defects of a silicon gate of a CMOS process. The method comprises the following steps: designing a comb-shaped testing structure of a parametric transistor according to an orthogonal table L9 (34), and detecting leakage defects between a source electrode and a drain electrode of the transistor when the silicon gate is a control gate pole; designing a through-hole chain-type testing structure of the parametric transistor according to an orthogonal table L16 (45), and detecting broken circuit defects when the silicon gate and an upper metal are connected with each other; designing a snake-shaped testing structure of a parametric phase inverter according to an orthogonal table L16 (45), and detecting the broken circuit defects when the silicon gate is the gate pole for interconnection; and measuring an optical parameter of each testing structure by using a four electrode testing method, and analyzing the level combination of factors which remarkably affect the random defects of the silicon gate through a variance analysis method. The basic units of the testing structures are arranged by a compact mode, can effectively utilizes areas of the testing structures, and can emulate the defects of the silicon gate in an actual circuit, thereby determining the level combination of the factors which remarkably affect the optical parameters of the testing structures.

Description

technical field [0001] The invention relates to a method for detecting random defects of a silicon gate in a CMOS process, and belongs to the field of integrated circuit manufacturing. Background technique [0002] In the process of integrated circuit manufacturing, due to various uncertain reasons, there are differences between the silicon gate on the chip and the expected silicon gate in the design, which is manifested as the unexpected absence or increase of silicon material in the silicon gate, and the electrical performance is manifested as an abnormal increase in resistance or decrease. The change of silicon gate resistance will affect the performance and function of the chip, and affect the yield of the chip. [0003] These defects appear as random probabilistic events and are called stochastic defects. The causes of random defects in the silicon gate are: particles caused by machine wear, pollutants on the Wafer surface, impurities during polysilicon deposition, po...

AI Technical Summary

Problems solved by technology

When used as a transistor to control the gate, the defect of the silicon gate may lead to a short circuit between the source and drain of the transistor or an increase in leakage; when the silicon gate is connected to the upper metal through a via hole, the defect may cause an open circuit; cause short circuit or open circuit

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