Configurable processor architecture and control method thereof

Abstract

The invention discloses a configurable processor architecture. The architecture comprises configurable control parts and configurable parts which are connected with each other, wherein the configurable control parts are used to execute instruction and send out configuration information to the configurable parts, and the configurable parts are used to execute and process the task according to the configuration information. The invention also discloses a control method of the configurable processor. The method comprises the following steps: the configurable control parts send out the configuration information to the configurable parts and the configurable parts execute the corresponding operation according to the configuration information. The complex data processing operation is shifted into each configurable part and the configurable control parts are very simple so that no complicated instruction pipeline is needed to design and the multilevel fast instruction cache is not needed to add to increase the processor performance; and the configuration instruction can be realized through long instruction so as to simplify the configuration complexity caused by the numerical change of the configurable parts.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a configurable processor architecture and a control method. Background technique [0002] As the integrated circuit manufacturing process enters the 90nm-45nm stage, ASIC (Application Specific Integrated Circuit) design for data flow algorithms (such as digital media and communication baseband, etc.) faces long design cycles, high design costs, and poor flexibility. , Poor scalability, it is difficult to meet the needs of rapid launch of products and continuous improvement of functions. [0003] The architecture and instruction system of existing processors, including CPU and DSP, have three problems: first, to realize high-performance arithmetic operation functions, a relatively complex architecture and instruction system must be required, and it is not easy to expand. In addition to the factors of technological progress, improving the computing performance from the arc...

AI Technical Summary

Problems solved by technology

[0002] As the integrated circuit manufacturing process enters the 90nm-45nm stage, the ASIC (Application Specific Integrated Circuit) design of data flow algorithms (such as digital media and communication baseband, etc.) faces long design cycles, high design costs, and poor flexibility. , poor scalability, it is difficult to meet the needs of rapid product launch and continuous improvement of functions

[0003] The architecture and instruction system of existing processors, including CPU and DSP, have three problems: first, to realize high-performance arithmetic operation functions, a relatively complex architecture and instruction system must be required, and it is not easy to expand. In addition to the factors of technological progress, improving the computing performance from the architecture often requires re-modifying the design of the entire processor, or even modifying the entire instruction system, such as adding computing components, storage components, and data paths; the second is the existing processing The performance improvement of the architecture of the processor needs to pay a large price in power consumption and area, because it mainly obtains performance improvement by increasing the execution speed of instructions, such as increasing the number of stages or lines of the pipeline, increasing the cache, etc., causing the processor The complexity of control components is rapidly increasing; the third is the implementation of algorithms based on the general processor instruction system. The disassembled program code has clear semantics and is relatively easy to be copied. It is difficult to guarantee the intellectual property rights of the core algorithm

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