Method for improving breakdown voltage of LDMOS devices

Abstract

The invention discloses a method for improving breakdown voltage of LDMOS devices, in the process of a front-segment preparation grid structure by adopting a conventional method, a grid structure is arranged above the area of an LDMOS device channel, is extended above a high-voltage drifting injection area and is separated from a field oxide area of the high-voltage drifting injection area; in the rear-segment process, a dielectric layer is sedimentated firstly, and then a conductor layer is sedimentated, and then the dielectric layer and the conductor layer are etched, the dielectric layer and the conductor layer above the high-voltage drifting injection area are kept to form a suspending grid electrode electric-conduction equipotential body, one end of the equipotential body is arranged on the field oxide area in the high-voltage drifting injection area, and the other end is arranged above the grid structure and between one side of a channel area and one side of a beak part of the field oxide area in the high-voltage drifting injection area. The method can be integrated in the PIP, MIP or RPOLY process and can be integrated in a metal connecting line process. The method in the invention can obviously improve the breakdown voltage of the LDMOS devices.

Description

technical field [0001] The invention relates to a preparation method of an LDMOS device, in particular to a method for increasing the breakdown voltage of the LDMOS device. Background technique [0002] In the current LDMOS (Laterally Diffused Metal Oxide Field Effect Transistor) device structure, the polysilicon gate is generally extended to the upper end of the field oxygen region, which can prevent the polysilicon from extending only to the LA region, because the thin gate oxide in the LA region is prone to leaks. The voltage difference between the region and the gate is easier to break down, resulting in a problem with a smaller breakdown voltage of the device. figure 1 Shown is a common LDMOS device structure, in which the width LCH of the channel region is formed by the overlapping region of polysilicon and the low-voltage P well; the LA segment is the region on the drain region from the channel region to the field oxide region , including the beak part of the field o...

AI Technical Summary

Problems solved by technology

However, in this structure, there are also unavoidable problems, that is, because the gate is an equipotential body, the electric force line will be nearly perpendicular to its surface, and the equipotential line will be nearly parallel to its surface, so that from the junction of PF and PA The potential lines will extend to the bird's beak in a direction nearly parallel to the field oxygen region, while the gate potential is zero, which will cause a large voltage drop across the thin gate oxide in the bird's beak region, so this structure will still Limiting further increases in device breakdown voltage

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