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Method for producing chip electrode multilevel interconnection structure

A multi-layer interconnection and chip electrode technology, applied in the field of biomedical engineering, can solve the problem of high process cost, and achieve the effect of increasing the number of interconnections and reducing the process cost

Inactive Publication Date: 2012-08-22
SHANGHAI JIAO TONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

And this process uses silicon as the substrate, and the process cost is relatively high

Method used

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  • Method for producing chip electrode multilevel interconnection structure
  • Method for producing chip electrode multilevel interconnection structure
  • Method for producing chip electrode multilevel interconnection structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0017] Such as figure 1 Shown, the present embodiment is prepared through the following steps:

[0018] The first step is to spin-coat photoresist on the silicon wafer and pattern the photoresist;

[0019] Said spin-coating photoresist refers to spin-coating AZ 4903 photoresist at a speed of 1900 rpm for 60 seconds.

[0020] The patterned photoresist refers to developing for 150 seconds with AZ-400K developer after exposure.

[0021] The second step is to place the chip on the determined position on the silicon wafer, and deposit a polymer film to fix the chip;

[0022] The deposition polymer refers to chemical vapor deposition parylene.

[0023] The thickness of the polymer film is 2-4 μm.

[0024] In the third step, the polymer is poured on the silicon wafer with the chip fixed as the substrate, and the polymer is cured.

[0025] The polymer is polydimethylsiloxane.

[0026] The cured polymer is baked in an oven at 80° C. for 3 hours.

[0027] The fourth step is to pe...

Embodiment 2

[0037] Such as figure 2 Shown, the present embodiment is prepared through the following steps:

[0038] The first step is to spin-coat photoresist on the silicon wafer and pattern the photoresist;

[0039] Said spin-coating photoresist refers to spin-coating AZ 4903 photoresist at a speed of 1900 rpm for 60 seconds.

[0040] The patterned photoresist refers to developing for 150 seconds with AZ-400K developer after exposure.

[0041] The second step is to place the chip on the determined position on the silicon wafer, and deposit a polymer film to fix the chip;

[0042] The deposition polymer refers to chemical vapor deposition parylene.

[0043] The thickness of the polymer film is 2-4 μm.

[0044] In the third step, the polymer is poured on the silicon wafer with the chip fixed as the substrate, and the polymer is cured.

[0045] The polymer is polydimethylsiloxane.

[0046] The cured polymer is baked in an oven at 80° C. for 3 hours.

[0047] The fourth step is to p...

Embodiment 3

[0057] Such as image 3 Shown, the present embodiment is prepared through the following steps:

[0058] The first step is to spin-coat photoresist on the silicon wafer and pattern the photoresist;

[0059] Said spin-coating photoresist refers to spin-coating AZ 4903 photoresist at a speed of 1900 rpm for 60 seconds.

[0060] The patterned photoresist refers to developing for 150 seconds with AZ-400K developer after exposure.

[0061] The second step is to place the chip on the determined position on the silicon wafer, and deposit a polymer film to fix the chip;

[0062] The deposition polymer refers to chemical vapor deposition parylene.

[0063] The thickness of the polymer film is 2-4 μm.

[0064] In the third step, the polymer is poured on the silicon wafer with the chip fixed as the substrate, and the polymer is cured.

[0065] The polymer is polydimethylsiloxane.

[0066] The cured polymer is baked in an oven at 80° C. for 3 hours.

[0067] The fourth step is to pe...

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Abstract

The invention relates to a method for producing a chip electrode multilevel interconnection structure in the technical field of biomedicine. The method has the following steps: imaging photo resist on a substrate to determine the position of a chip; placing the chip on the substrate and then depositing a layer of thin polymer film on the surface of the chip by chemical vapor deposition to fix thechip; pouring a polymer layer with a thickness of 500 mu m outside the position of the chip on the substrate, carrying out curing process on the polymer layer, stripping off the substrate to cause the chip to be coated by the polymer layer; and afterwards, carrying out the following steps repeatedly by n numbered times in sequence on the whole surface of the polymer layer: sputtering and imaging the metal layer, depositing the thin polymer film with a thickness of 6-8 mu m by chemical vapor deposition and imaging the thin polymer film to realize multilevel chip electrode interconnection, wherein n is a constant which is equal to or more than 3.The structure of the invention can greatly increase interconnection of the chip and electrodes per unit area, enhances the effect of electrode stimulation and collection and can be conveniently used in artificial prosthesis devices.

Description

technical field [0001] The invention relates to a method in the field of biomedical engineering, in particular to a method for preparing a chip electrode multilayer interconnection structure. Background technique [0002] Artificial prostheses are used to treat and restore certain human organs that have lost their functions. For example, visual prostheses can help patients restore their vision, and cochlear implants can help patients restore their hearing. As a system implanted into the human body, an artificial prosthesis generally consists of a control chip and electrodes. The direct interconnection of chips and electrodes can not only reduce the volume of the entire system, but also make the system more convenient when implanted in the body and reduce trauma to the human body. Single-layer chip electrode interconnection, the number of electrodes connected to the chip per unit area is limited. Multi-layer chip electrode interconnection can make the number of electrodes c...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/52H01L21/768
Inventor 刘景全芮岳峰杨春生闫肖肖唐刚
Owner SHANGHAI JIAO TONG UNIV
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