Test data compression method of integrated circuit test

Abstract

The invention provides a test data compression method of an integrated circuit test, which adopts an original test data storing law and then reduces the original test data storing law to obtain needed original test data when the test is applied, that is to say, the storage of the integral original test data is changed into the storage of one or a plurality of corresponding irrational numbers. The test data compression method of the integrated circuit test particularly comprises the following steps of: generating a determined complete test set recorded as a test vector set by adopting an automatic test mode generation tool; cascading all test vectors; filling independent bits; counting a run-length; transforming into decimal numbers; and transforming into the irrational numbers. The invention has the advantages of theoretically unlimitedly compressing the test data by changing the storage of codes of the integral test set into the storage of an encoding law and fundamentally solving the problem of storage of the test data.

Description

【Technical field】 [0001] The invention relates to an integrated circuit testing technology, in particular to a method for compressing test data in a built-out self-test (Built-Out Self-Test, BOST) method for a system chip (System-on-a-Chip, SoC). 【Background technique】 [0002] The development of integrated circuit technology makes it possible to integrate hundreds of millions of devices in one chip, and can integrate pre-designed and verified IP, such as memory, microprocessor, DSP, etc. Such a diversified integrated chip has become an integrated system capable of processing various information, and is called a system on chip or system chip (SoC). SoC greatly reduces the system cost, shortens the design cycle, and speeds up the time to market, but the testing of SoC products faces more and more challenges, such as: [0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be tested t...

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Problems solved by technology

[0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be tested through the limited input / output pins of the chip, and it is difficult to directly control or observe the internal nodes of the chip through macro mechanical devices.

[0004] 2. Automatic test equipment (ATE) is expensive, and the development speed of chip design and manufacturing technology is faster than that of ATE. The clock frequency of the chip has exceeded the frequency of the most advanced ATE at present, and full-speed testing cannot be performed.

[0005] 3. The amount of test data is large. The more IP integrated in the SoC, the greater the amount of test data required

[0010] In the traditional method, these seeds or code words (compressed form) are all directly (statically) stored in the ATE memory, and the storage capacity it occupies will increase with the increase of the original test data volume, although the ATE The storage is in a compressed form, but its volume is still large, so the increasing amount of test data poses a challenge to ATE storage